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Modeling >> Semiconductor Devices >> on current reduces below e-11 when interface trap is introduced
https://designers-guide.org/forum/YaBB.pl?num=1391801935

Message started by biju4u90 on Feb 7^th, 2014, 11:38am

Title: on current reduces below e-11 when interface trap is introduced
Post by biju4u90 on Feb 7^th, 2014, 11:38am

why the on current reduces to e-11 order from e-6 order when an interface trap level is introduced in SiC power mosfet??

Title: Re: on current reduces below e-11 when interface trap is introduced
Post by Geoffrey_Coram on Feb 25^th, 2014, 12:52pm

I don't think you've given us enough information to understand your question. Are you talking about introducing an interface trap level in the device model for the mosfet? or doing something in the fabrication of the device?

Title: Re: on current reduces below e-11 when interface trap is introduced
Post by biju4u90 on Mar 9^th, 2014, 9:07pm

Yes. The problem occured while trying to introduce interface traps in mosfet. its not fabrication, just simulation using atlas

Title: Re: on current reduces below e-11 when interface trap is introduced
Post by biju4u90 on Mar 9^th, 2014, 9:08pm

is there any limitation for the oxide thickness that can be used while introducing interface traps in a mosfet simulation?