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Design Languages >> Verilog-AMS >> Simulating Verilog-A and Verilog-D together
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Message started by mowiehowie on Feb 28^th, 2014, 8:49am

Title: Simulating Verilog-A and Verilog-D together
Post by mowiehowie on Feb 28^th, 2014, 8:49am

Hello,
Anyone could help me to find out how can I simulate Verilog-A and Verilog-D modules instantiated in the same schematic when using Virtuoso ADE ?
Any tutorials ?
Thanks,

Title: Re: Simulating Verilog-A and Verilog-D together
Post by Andrew Beckett on Feb 28^th, 2014, 9:40am

These are in the documentation. If using IC615 or IC616 (say), in the CIW, you can do Help->Virtuoso Documentation, and then expand "AMS Environment" and then "Virtuoso AMS Designer Environment Tutorials".

The tutorial databases are at <ICinstDir>/tools/dfII/samples/tutorials/AMS - there are a number of gzipped tar files in there and a PDF. In particular AMSDInADE.tar.gz is a good place to start.

The tutorials are in the same place in IC5141 too.

Regards,

Andrew.