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Design Languages >> Verilog-AMS >> Problem with Analog Sensitivity to Digital Events
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Message started by Zorro on Mar 6^th, 2014, 1:41am

Title: Problem with Analog Sensitivity to Digital Events
Post by Zorro on Mar 6^th, 2014, 1:41am

Dear Members,

well it's been a long time since my last post and since I was using verilogams.

Now I have a to do a simple model but somehow I cannot figure out what is wrong as the code is not working as I expect it to do. Hopefully you can help me out to find the error.

The basic concept is 1bit dac i.e. the input is a digital signal (1bit) that must be converted into an analog signal.

I want to use "Digital Access on Demand", in more detail "Analog Sensitivity to Digital Events"

As a reference I am using the book "The Designer's Guide to VerilogAMS" by Kenneth S. Kundert", section 3.2.2, page 116, "Analog Sensitivity to Digital Events", Listing 11.

Here is my code:

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns/1ps

module dac_1bit_model1 ( out_ana, in_dig);

inout out_ana;
electrical out_ana;

inout in_dig;
logic in_dig;

real value_ana;

analog begin

@(posedge in_dig) value_ana = 1.2;
@(negedge in_dig) value_ana = 0.0;
@(initial_step) value_ana = (in_dig ? 1.2 : 0.0);

V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n);

end

endmodule

Well, for me the code looks ok.

As you can see from pict1 the sensitivity to the events in signal "in_dig" is not working properly because the real variable "value_ana" is corrupt and therefore the transition to V(out_ana) is also corrupt.

I was thinking of possible reasons:

1. I need to include following lines inside the analog block in order to increase the accuracy:

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns/1ps

module dac_1bit_model1 ( out_ana, in_dig);

inout out_ana;
electrical out_ana;

inout in_dig;
logic in_dig;

real value_ana;

analog begin

@(posedge in_dig)
;

@(negedge in_dig)
;

@(posedge in_dig) value_ana = 1.2;
@(negedge in_dig) value_ana = 0.0;
@(initial_step) value_ana = (in_dig ? 1.2 : 0.0);

V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n);

end

endmodule

the problem is that I have tried this already and I see no difference in the results.

2. I also tried out this code:

`include "constants.vams"
`include "disciplines.vams"
`timescale 1ns/1ps

module dac_1bit_model1 ( out_ana, in_dig);

inout out_ana;
electrical out_ana;

inout in_dig;
logic in_dig;

real value_ana;

analog begin

@(posedge in_dig)
$discontinuity(0);

@(negedge in_dig)
$discontinuity(0);

@(posedge in_dig) value_ana = 1.2;
@(negedge in_dig) value_ana = 0.0;
@(initial_step) value_ana = (in_dig ? 1.2 : 0.0);

V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n);

end

endmodule

but results are identical.

3. Accuracy Settings, may be I have to change some tool accuracy settings, but I think this is not the problem. So here I have not done any attempt.

I am very happy about your suggestions, comments.

Regards!
Douglas

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Zorro on Mar 6^th, 2014, 5:26am

Hi All again,

I could find a temporary solution. However this is not exactly the approach that I wanted to use and it is still not working fine.

I wanted to sense the "digital events" while being inside the "analog process" so that I can call it "Analog Sensitivity to Digital Events" as explained in the book.
Unfortunately it is not working properly. May be something is missing and I still need support or suggestions about how to do this.

For example in another code I could make "Digital Sensitivity to Analog Events" and it was working fine, like this:

always @(cross(V(in_ana)-vddc_high/2, -1)) fork
t1 = $realtime;
in_ana_is_low_is_low = 1;
join

always @(in_ana_is_low_is_low) begin
#(td) flag1 = 1;
end

In the temporary solution I am sensing the "digital events" outside the "analog process" and therefore they are being sensed inside the "digital proces".
This is working and it is fine. But this is not what I wanted to try and verify.

This is my temporary solution (which cannot be called "Analog Sensitivity to Digital Events").
The real variable "value_ana" seems to be ok now but there is a problem when passing it to the "analog domain" and I cannot explain why.

`include "constants.vams"
`include "disciplines.vams"

module dac_1bit_model2 ( out_ana, in_dig);

output out_ana;
electrical out_ana;

input in_dig;
logic in_dig;

real value_ana;

initial begin
value_ana = (in_dig ? 1.2 : 0.0);
end
always @(posedge in_dig) value_ana = 1.2;
always @(negedge in_dig) value_ana = 0.0;

analog begin

V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n);

end

endmodule

Please give me a hint if you have any suggestion to implement correctly "Analog Sensitivity to Digital Events" or to correct the temporary solution. Thank you!

Regards!
Douglas

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by boe on Mar 6^th, 2014, 6:54am

Zorro,
model2 is correct and working as expected because transition filter should have discrete (and not continuous as in model1) input.
- B O E

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Zorro on Mar 6^th, 2014, 7:39am

Hi BOE,

thanks for your feedback.

Do you have any hint about how can I transfer/assign the variable "value_ana" to the electrical pin "out_ana" without distortion?
This is not working and that is the task of the model, to convert a "digital" clock into an "analog" clock.

You say:
"model2 is correct and working as expected because transition filter should have discrete (and not continuous as in model1) input."

but

1. The transition filter is not working. See pict2 and scroll down. May be you are not seeing signal "out_ana".

2. In Kennet Kundert's book, section 3.1, page 114 towards the bottom I can read:

always @(posedge clk)
begin
...
a=1;
end

would mean that the real variable is ouned by the digital kernel. Other assignments to "a" would be allowed in the digital context like in other "always" or in "initial" blocks,
but assigments to "a" in the analog process would be illegal. However "read-access" to "a" would be allowed in both contexts.

That is exactly what I am doing (but it is not working). In the analog process I am only "reading" the variable "value_ana" which I know that is owned by the digital kernel.
I understand that this is allowed as I am not assigning a new value to "value_ana" inside the analog process, rather than that I am only "reading" or "using" the value of
the variable inside the analog process and "read-access" is allowed in both contexts.

Thanks for any suggestion.

Regards,
Douglas

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by boe on Mar 6^th, 2014, 8:29am

Hi Zorro,
I just tested it. model2 works. Maybe you're using an old/buggy tool version?
- B O E

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Zorro on Mar 6^th, 2014, 9:10am

Hi BOE,

could you plot following signals and post a picture please?

out_ana electrical signal
in_dig digital signal
value_ana variable that is owned by the digital kernel

the problem that I have is when I do this:

analog begin
V(out_ana) <+ transition(value_ana, 0.0, 1n, 1n);
end

in my case the contribution to the "out_ana" signal is not correct as you can see in pict2.

Then I will have to check the settings.

Regards,
Douglas

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Zorro on Mar 6^th, 2014, 11:19pm

Hi All,

I am using cadence 6.1.5 so I do not think that the problem is because the software is outdated. :(

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by boe on Mar 7^th, 2014, 12:21am

Zorro wrote on Mar 6^th, 2014, 9:10am:

Hi BOE,

could you plot following signals and post a picture please?
...

Douglas,
as you can see, it works fine. I used Cadence ncsim 11.1 as simulator. If you are using an older version, you should consider changing to a newer version.

- B O E

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Ken Kundert on Mar 7^th, 2014, 3:01pm

Zorro,
Please disregard BOE's suggestion that you should use your model2. I would not expect that model to work well. However, I would think your model1, though perhaps overly complicated, should work well. I am surprised it is not, and I believe it is something that you should discuss with your simulator company. You may be stumbling over a bug. Having said that, there are ways you can improve your model and perhaps overcome the problem you are having. I would suggest using something like:

Code:

module dac_1bit_model (out_ana, in_dig);
output out_ana; electrical out_ana;
input in_dig; logic in_dig;

analog begin
@(posedge in_dig or negedge in_dig)
;

V(out_ana) <+ transition(in_dig ? 1.2 : 0.0, 0, 1u, 1u);
end
endmodule

Somethings to notice about this implementation:

The @(...) controls the timestep in the analog simulator, forcing it to place time points at changes in the digital input. In this way, no changes in the digital input should be missed.
The output is produced by a transition function, meaning that the transitions will be well controlled. (This seems to be the problem you are having, your transitions are not well controlled.)
The output is computed on every analog timestep using "in_dig ? 1.2 : 0.0", making the model more robust (no need to worry about initializing the state).
The digital value is tested using the ?: operator, eliminating any chance that an X value will get into the analog output signal.
I increased the transition time to 1us, which seems much more reasonable for the simulation you are running (using too small of a transition time can waste considerable simulation time).

-Ken

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Zorro on Mar 9^th, 2014, 6:53am

Hi Ken,

thanks for your reply. Unfortunately I will be able to check your suggestion until Tuesday when I am back in office.

I was also thinking that this could be a software issue because I could not explain myself what could be wrong in the code. For example in model2 I can see that there is in fact something wrong with the "transition".

I will need to use a transition time of tr=tf=1ns because the input clock signal has a period of 4us and having a rising/falling time of 1us would not work fine for this particular case.

For model's testing purposes using tr=tf=1ns is ok. When I am sure that I have full control of the behavior I will use tr=tf=0.1us=100ns to reduce simulation time.

I will post my results as soon as I have tried your suggestions.

Regards!
Douglas

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Zorro on Mar 11^th, 2014, 12:47pm

Hi Ken,

I have spent hours trying different approaches and combinations without success.

I am sorry to say that your suggested code is also not working.

It seems that there must be a bug in the software. I will contact CAD Support tomorrow so that they can have a look.

I will use your suggested code to show the error.

Attached some pictures and below the codes that I am using.

clk_gen

`include "constants.vams"
`include "disciplines.vams"
`timescale 1us/1ps

module clk_gen(clk);

output clk;
reg clk;

parameter real period = 4; // clock period (us)
parameter real td = 0.0; // delay (us)

initial begin
clk = 0;
#(td) clk = ~clk;
forever begin
#(period/2) clk = ~clk;
end
end

endmodule

dac_1bit_model8

`include "constants.vams"
`include "disciplines.vams"
`timescale 1us/1ps

module dac_1bit_model8 ( out, in);

inout out;
electrical out;

inout in;
logic in;

real value;

analog begin

@(posedge in or negedge in)
;

V(out) <+ transition(in ? 1.2 : 0.0, 0.0, 1n, 1n);

end

endmodule

Best Regards!
Douglas

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Zorro on Mar 11^th, 2014, 12:52pm

...and these are the simulation results:

fall time is to be ok = 1ns
rise time is not ok = 146ns

I wonder where this value trise=146ns comes from?

As I mentioned I have run several simulations and I have used different models and sometimes trise is wrong, sometimes tfall is wrong and sometimes both values are wrong i.e. arbitrary values can be read.

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Ken Kundert on Mar 13^th, 2014, 12:52am

Did you ever try setting the transition time to something not so extreme?

-Ken

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Zorro on Mar 13^th, 2014, 10:18am

Hi Ken, BOE, All,

well after some sessiones with support we found the root cause.

In my settings I was using this:

skipcount=2

If I choose the default values i.e. skipcount=0 everything is fine.

thanks to everybody for your time and support!

Below some details that could be interesting.

Douglas

"Within the transient simulation the options skipdc=yes and skipcount=2 are activated.
The simulation itself is event driven from the digital world. The analogue solver knows exactly when to calculate the analogue signal. This is done and then with skipcount every second point is saved.
The Viva loads the results and interpolate the pre event point with the post event point and it seems that the outputs reacts before something happens at the input.

If you set skipdc and skipcount to default the results are looking good."

scskipcount
Specifies a number of points and directs the simulator to save one point every time it calculates that number of points.

skipcount
The number of points to be calculated for each saved point.

Title: Re: Problem with Analog Sensitivity to Digital Events
Post by Ken Kundert on Mar 13^th, 2014, 4:39pm

There are a couple of lessons to be taken from this.

First, you should not be using skip count. One should only use skip count if the size of the simulation data file is problematic, and when you use it and you get unexpected results, you should always place it high among the list of likely perpetrators. There is a reason why the simulator computes all those time points, and ignoring half of them or more is a dubious practice that should only be used if you are desperate.

Second, you should always generate a simple example and give the complete example on this forum if you want people to help you. If you had given the model and the netlist, you would have gotten an answer to your problem right away.

Lastly, and this is for Cadence, not you, Spectre should always output the break points regardless of skip count. This is the "bug" I mentioned in my previous message. Perhaps you can pass this suggestion/bug report back to whomever you were talking to at Cadence.

-Ken