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Design >> Mixed-Signal Design >> comparator recommendations
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Message started by aaron_do on Mar 11^th, 2014, 10:22pm

Title: comparator recommendations
Post by aaron_do on Mar 11^th, 2014, 10:22pm

Hi all,

does anybody know of a good comparator design? I'm looking for the fastest, meanest, ugliest design around. Right now I'm using one similar to that detailed in "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs" IEEE ASSCC Nov 2008.

thanks,
Aaron

Title: Re: comparator recommendations
Post by AnalogDE on Mar 13^th, 2014, 4:32pm

Interesting paper.

I recently designed a pretty simple high speed comparator borrowing the basic circuit from a paper by Yin JSSC Feb 1992.

Basically a input diff pair followed by a cross-coupled latch with a pretty simple clocking circuit.

Title: Re: comparator recommendations
Post by aaron_do on Mar 13^th, 2014, 6:06pm

Thanks for the tip. I had a look at it, but I'm not sure it would be as fast as the one I'm using...I also tried the strongarm comparator, and the one I'm using turned out to be around 2x faster...

thanks,
Aaron

Title: Re: comparator recommendations
Post by loose-electron on Mar 26^th, 2014, 11:39am

latching or not?
clocked or not?

Some of the most efficient designs integrate the comparator with the next stage latch

Title: Re: comparator recommendations
Post by aaron_do on Mar 26^th, 2014, 8:02pm

Clocked and Latched.

Basically the one I'm using has a first stage "dynamic preamp" and a second stage latch. The dynamic preamp's output is reset to VDD with PMOS transistors, and then on the clk signal, the input diff-pair turns ON and the PMOS load turns OFF which pulls the output CM down to ground with some differential gain along the way. About halfway down, the preamp triggers the next stage latch. Because the PMOS load is OFF, the gain of the preamp is very high and it uses little power because it is dynamic.

Aaron