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Design Languages >> Verilog-AMS >> Parent Child Instantiation
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Message started by Davivilla on Mar 21^st, 2014, 9:05am

Title: Parent Child Instantiation
Post by Davivilla on Mar 21^st, 2014, 9:05am

Hi

I am working in cadence IC 5.1 and i need to do a module with submodules, but in the language reference manual the example is not clear. can you help me?

This is the example of LRM of verilog-a.

module comparator(cout, inp, inm);
output cout;
input inp, inm;
ground gnd;

electrical cout, inp, inm;

parameter real td = 1n, tr = 1n, tf = 1n;
real vcout;

analog begin
@(cross(V(inp) - V(inm), 0))
vcout = ((V(inp) > V(inm)) ? 1 : 0);
V(vcout) <+ transition(vcout, td, tr, tf);

end
endmodule

module integrator(out, in);

output out;
input in;

electrical in, out;

parameter real gain = 1.0;
parameter real ic = 0.0;

analog begin
V(out) <+ gain*idt(V(in), ic);
end
endmodule

module sigmadelta(out, ref, in);
output out;
input ref, in;
comparator C1(.cout(aa0), .inp(in), .inm(aa2));
integrator #(1.0) I1(.out(aa1), .in(aa0));
comparator C2(out, aa1, gnd);
d2a #(.width(1)) D1(aa2, ref, out);// A D/A converter

endmodule

Why the parent module is instiantiated at the end?
If i create this example cadence only recognize the fisrt module as parent.
Does parent module need to have a symbol?
Does All the modules needs to be created with symbol?
Does the modules need to be in any special place?, like the same library.
Can the parent module contain some description or only the instantiation?

Title: Re: Parent Child Instantiation
Post by boe on Mar 21^st, 2014, 10:06am

Davivilla wrote on Mar 21^st, 2014, 9:05am:

Hi

I am working in cadence IC 5.1 and i need to do a module with submodules, but in the language reference manual the example is not clear. can you help me?

...

Why the parent module is instiantiated at the end?

Why not?

Quote:

If i create this example cadence only recognize the fisrt module as parent.

Every module should be defined as its own cell.

Quote:

Does parent module need to have a symbol?

If you want to use it in a schematic, yes.

Quote:

Does All the modules needs to be created with symbol?

No.
Quote:

Does the modules need to be in any special place?, like the same library.

Same library makes sense, but is probably not necesary [never tried that].

Quote:

Can the parent module contain some description or only the instantiation?

Yes, you can add as many comments as you like.

- B O E

Title: Re: Parent Child Instantiation
Post by Davivilla on Mar 21^st, 2014, 10:26am

Hi B O E,

Thank you,

The problem is when i save the model, cadence recognize the first module instantiation as a parent. But obviosly the parent is at the end.
Then the symbol of the model has the imputs and outputs of the first module instatntion.

Best regards

Title: Re: Parent Child Instantiation
Post by Geoffrey_Coram on Mar 24^th, 2014, 12:26pm

I think BOE was suggesting that each module definition should be placed in a separate file, then it won't be a problem that only the first module in the file is recognized. It's a little more work to create the files, but shouldn't be too onerous.

Title: Re: Parent Child Instantiation
Post by Davivilla on Mar 25^th, 2014, 6:29am

Thank you Geoffrey_Coram.

I want to take a look at this code.
This is the parent:

Code:

This is the child1:

Code:

module hijo1(entrada, salida);

inout entrada, salida;
electrical entrada, salida;

parameter gain=10;

analog begin

V(salida)<+ gain*V(entrada);

end

endmodule

And this is the child2:

Code:

module hijo2(in, out);

inout in, out;
electrical in, out;

parameter polo1=10;

analog begin

V(out)<+laplace_np(V(in),{10},{6.28e-6, 0, 62.8e-9,0});

end

endmodule

All modules are created in the same library.
Everyone has an associated symbol.
The final code is the union of all in that order ie.

Code:

// VerilogA for test_zjerarquia, padre, veriloga

`include "constants.vams"
`include "disciplines.vams"

module padre(entra, sale);
inout entra,sale;
electrical entra,sale;

hijo1 h1(entra, in);
hijo2 h2(salida,sale);

endmodule

// // // // // // // // // // // // // // // // // //
// // // // // // // // // // // // // // // // // //
// // // // // // // // // // // // // // // // // //

module hijo1(entrada, salida);

inout entrada, salida;
electrical entrada, salida;

parameter gain=10;

analog begin

V(salida)<+ gain*V(entrada);

end

endmodule

// // // // // // // // // // // // // // // // // //
// // // // // // // // // // // // // // // // // //
// // // // // // // // // // // // // // // // // //
module hijo2(in, out);

inout in, out;
electrical in, out;

parameter polo1=10;

analog begin

V(out)<+laplace_np(V(in),{10},{6.28e-6, 0, 62.8e-9,0});

end

endmodule
// // // // // // // // // // // // // // // // // //
// // // // // // // // // // // // // // // // // //
// // // // // // // // // // // // // // // // // //

finally when i simulate, i do not get results.

Thank you and
Best regards

Title: Re: Parent Child Instantiation
Post by Davivilla on Mar 27^th, 2014, 8:46am

Hi

Look guys I found the solution for those who may be of interest.
The solution is create a unique the module for parent.
This module should contain only the mapping of ports and parameters of the child.
Th The syntax for this issue is:

Code:

`include "constants.vams"
`include "disciplines.vams"

module padre(entra, sale);
inout entra,sale;
electrical entra,sale;
parameter carrier=1;
parameter gan2=1;

electrical aa; // wire

hijo1 #(.gain(carrier)) h1(entra, aa);
hijo2 #(.gain2(gan2)) h2(aa,sale);

endmodule

Thank you all for the help.