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Measurements >> Phase Noise and Jitter Measurements >> Phase Noise Simulation of Frequency Multiplier Using Jitter/Timedomain Noise
https://designers-guide.org/forum/YaBB.pl?num=1396361186

Message started by Dave Rittel on Apr 1^st, 2014, 7:06am

Title: Phase Noise Simulation of Frequency Multiplier Using Jitter/Timedomain Noise
Post by Dave Rittel on Apr 1^st, 2014, 7:06am

Hello All,

I have simulated the phase noise of frequency dividers in the past numerous times using the method defined in Chapter 6 of "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers" by Ken Kundert.

I believe that I could use the same method to run the phase noise on a frequency multiplier, but I'm having trouble finding a reference. Does anybody have experience running phase noise simulations on frequency multipliers or know of a reference?

I'm basically following the directions as described in the frequency divider chapter (Chapter 6) with a couple changes. I'm doubling a 100MHz input to a 200MHz output. The beat frequency is 100MHz, and I'm doing a relative sweeptype in pnoise and looking at the noise at the 2nd harmonic. Other than that, I believe the method is the same. I define a zero crossing in pnoise and look at the noise there. From there, I calculate the phase noise from the output frequency, the slew rate at the zero crossing, and the zero-crossing noise.

Thanks in advance for your help,
Dave

Title: Re: Phase Noise Simulation of Frequency Multiplier Using Jitter/Timedomain Noise
Post by tm123 on Apr 15^th, 2014, 9:58am

Dave,

Interesting question, I have not thought about simulating noise of frequency multipliers. I was hoping Ken would comment on this, and if the sampled noise approach would apply for multipliers as well as dividers.

Good luck,
Tim