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Design >> Mixed-Signal Design >> Clock divider.
https://designers-guide.org/forum/YaBB.pl?num=1396472620

Message started by Jacki on Apr 2^nd, 2014, 2:03pm

Title: Clock divider.
Post by Jacki on Apr 2^nd, 2014, 2:03pm

Hi,

I want to get a clock divider as shown in the figure, does anybody know how to do it with the basic digital logic blocks like DFF, AND gate, OR gate ...

Thank you.

Title: Re: Clock divider.
Post by Jacki on Apr 2^nd, 2014, 2:07pm

The duty cycle is not 50%, I try to use clock divider by 5, or counter to achieve it, but I failed.

Title: Re: Clock divider.
Post by AnalogDE on Apr 2^nd, 2014, 3:28pm

This looks pretty simple. You can do it with a counter with output logic that decodes the 'count'. Logic outputs a '1' when it hits its 'count' that it decodes. Run that logic and AND it with incoming clock... That should be it.

Title: Re: Clock divider.
Post by Jacki on Apr 2^nd, 2014, 6:29pm

Hi AnalogDE,

Thank you very much for your reply. I don't follow you very well. I will make a test tomorrow. Could you show me a logic structure (building block) as you are convenient?

Title: Re: Clock divider.
Post by Jacki on Apr 3^rd, 2014, 12:33pm

Hi AnalogDE,

I understand what you mean, thank you.