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Design Languages >> Verilog-AMS >> $random always generates the same value
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Message started by Lucho on Apr 8^th, 2014, 1:11pm

Title: $random always generates the same value
Post by Lucho on Apr 8^th, 2014, 1:11pm

Hi have the following verilog-a block for a random number generator:

--

// VerilogA for Example, RdnGen, veriloga

`include "constants.vams"
`include "disciplines.vams"

module RdnGen(out);

output out;
electrical out;

integer randn;
integer sign;

analog begin

randn = $random %60;
sign = (randn < 0) ? 1:-1;

@(initial_step)

$strobe

("Rand\t\t",randn,
"\n", "Sign\t\t", sign,
"\n\n\n\n\n");

end
endmodule
~

--

I don't understand why every single time I run this code the "randomly" generated number is always the same.

Any hints ?

Thank you,

Title: Re: $random always generates the same value
Post by Andrew Beckett on Apr 9^th, 2014, 11:21pm

The seed is such that simulations are reproducible - you run the same simulation twice, you'll get the same answer.

Andrew.

Title: Re: $random always generates the same value
Post by Lucho on Apr 10^th, 2014, 11:20am

Thank you very much for your answer,

However, we've observed that for IC5.1 that is not the case, as for each DC op point simulation we obtain a different randomly generated number. This issue has appeared in the virtuoso 6.1.5 version.

As a secondary question, what would be an alternative then to obtain a randomly generated sign (+ or -) for a signal that would be used as a DC offset for an amplifier model ?

Regards,

Lucho.

Title: Re: $random always generates the same value
Post by Geoffrey_Coram on Apr 16^th, 2014, 10:51am

The LRM says
"The random_seed argument may take one of several forms. It may be omitted, in which case the simulator picks a seed."

It sounds like the simulator changed how it picks the seed between the different versions.

To work around this, you'll need to specify a seed, probably by passing in the trial number of the simulation.