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Modeling >> Semiconductor Devices >> Why Nwell on SOI substrate?
https://designers-guide.org/forum/YaBB.pl?num=1397399993

Message started by ywguo on Apr 13^th, 2014, 7:39am

Title: Why Nwell on SOI substrate?
Post by ywguo on Apr 13^th, 2014, 7:39am

Hi Guys,

Why is there nwell on SOI substrate? I thought nwell is not necessary to build NMOS and PMOS on SOI substrate. To my surprise, there is nwell in SOI technology. And PMOS is inside nwell in standard cells for that process. Why? Thank you in advance.

Best Regards,
Yawei

Title: Re: Why Nwell on SOI substrate?
Post by aaron_do on Apr 14^th, 2014, 6:01am

Hi,

I might not be thinking straight at the moment, but as I remember, there's more than one type of SOI. There's one where its basically just standard CMOS with an insulator underneath, and then the deep trench isolation goes all the way down to the oxide layer (the SOI layer). For that type, the diffusion doesn't come close to reaching the buried oxide. The buried oxide is just good for improving isolation. Maybe this is the type you are using.

Then there's another kind of SOI where the buried oxide is much more shallow, and the diffusion actually abuts the oxide. This kind of SOI has significantly less junction capacitance since only the "channel-side" of your diffusion faces the body. It also has good isolation. I think maybe this is the one where you think there doesn't need to be an nwell? So you just want to use n-diffusion to create the channel? Even with this kind of SOI, the PMOS transistors may not be created like that but I have no idea...

Its been a while, so I've forgotten the names of these two variants of SOI. You should be careful which one you choose because there's a huge difference in performance between the two. There's also other options for SOI such as the buried oxide depth, and also since last year or the year before there was an SOI technology with a special layer just under the buried oxide which helps to reduce distortion (again its been a while and I can't remember the details). You should ask the foundry about their process, cos if they don't offer the newer better SOI, they might simply not tell you :P

regards,
Aaron

EDIT:
Now that I'm awake, the first one I described is called thick-film SOI, and the second one is called thin-film SOI. There is also partially-depleted and fully-depleted SOI and according to some people I've talked with, they're not exactly the same thing, but to me they seem to be very similar...I think thin-film is always fully-depleted, and thick-film is always partially depleted (don't quote me on that).

Title: Re: Why Nwell on SOI substrate?
Post by sheldon on Apr 14^th, 2014, 7:37pm

Yawei,

Could this source of confusion just be the naming convention?
Usually the Silicon layers are doped eithe p-type or n-type and
counter-doping is used to create a complementary substrate
region. Don't think that changes just because the wafer is SOI.
So what you are calling n-well is more like an n-island where
a p-channel device will be built. As compared to the native,
p-island, where n-channel devices are built.

Sheldon

Title: Re: Why Nwell on SOI substrate?
Post by ywguo on Apr 15^th, 2014, 12:39am

Hi Aaron and Sheldon,

Thank you very much. I got a training material yesterday. Indeed nwell is required to reverse the doping of PMOS body. I think the silicon layer above the oxide is p-type or native. So it needs nwell doping to become PMOS body.

The process is a partial-depleted SOI.

Yawei