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Simulators >> Circuit Simulators >> ASSURA Post layout simulation error
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Message started by VINAY RAO on Apr 16^th, 2014, 1:25am

Title: ASSURA Post layout simulation error
Post by VINAY RAO on Apr 16^th, 2014, 1:25am

Hello all,
I have designed and lay-outed cascode LNA and also extracted parasitics using Assura QRC. Each flow passed without any error. But post layout simulation using hierarchy editor with av_extracted view giving following error in CADENCE ADEL.

"Error found by spectre in `LPNA', during circuit read-in.
ERROR (SFE-23): "input.scs" 19: c1 is an instance of an undefined model cmodel.
ERROR (SFE-23): "input.scs" 20: c2 is an instance of an undefined model cmodel.
. . . . . .
. .. . . . .
ERROR (SFE-23): "input.scs" 137: rb1 is an instance of an undefined model ME8_C.
ERROR (SFE-23): "input.scs" 138: rb2 is an instance of an undefined model ME8_C.
ERROR (SFE-23): "input.scs" 139: rb3 is an instance of an undefined model ME8_C."

Where these resistors (rb1,rb2,rb3 etc..) and capacitors(c1,c2 etc) are actually layout parasitics and that are created by ASSURA itself. Assura has taken these passives from analogLib for extraction.

How this can be resolved? I am using UMC 65nm. I have attached QRC log file as well. Thank you.

Regards,
Vinay Rao.

Title: Re: ASSURA Post layout simulation error
Post by Andrew Beckett on Apr 16^th, 2014, 8:32pm

Hi Vinay,

On the QRC form, go to the "Netlisting" tab. Make sure that both Parasitic Capacitor Models and Parasitic Resistor Models are set to either "Include as Comment" or "Do Not Include" (i.e. not "Include Model"). It's the "Include Model" that will be setting the model parameter on the parasitic components.

Regards,

Andrew.

Title: Re: ASSURA Post layout simulation error
Post by VINAY RAO on Apr 17^th, 2014, 12:36am

Andrew, I sincerely thank you for saving much of my time. Yes indeed that is the reason why it was giving such errors.

Regards,
Vinay Rao.