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Design >> Mixed-Signal Design >> How to generate the synchronized clock signals for two different grounds.
https://designers-guide.org/forum/YaBB.pl?num=1397838411

Message started by Jacki on Apr 18^th, 2014, 9:26am

Title: How to generate the synchronized clock signals for two different grounds.
Post by Jacki on Apr 18^th, 2014, 9:26am

Hello,

I am facing a critical problem of generating the synchronized clock signals for two analog circuits which have different grounds.
As shown in the attached figure, the clock generator has the single input clock signal from outside. The clock generator should send two different control signals to two analog blocks. The challenge here is the two analog blocks have different grounds, one (ANA_1) is the same as clock generator, it is fine. But the other (ANA_2) has higher ground voltage, I really don't know how to design the control signal for ANA_2. The control signals for ANA_1 and ANA_2 should be synchronized.
Does anyone have possible solutions to solve this problem? I appreciate any comments about it, even somebody can tell me this idea doesn't work at all.
Thank you.

Title: Re: How to generate the synchronized clock signals for two different grounds.
Post by Shady Adly on Apr 22^nd, 2014, 7:13am

A simple solution would be to add an AC coupling capacitor between the clock generator and the block "ANA_2" followed by a self biased inverter/buffer referenced to ANA_2 rails, then you will have your clock with levels VSSA and VSSA+1.8V

Title: Re: How to generate the synchronized clock signals for two different grounds.
Post by Jacki on Apr 22^nd, 2014, 11:35am

Hello Shady Adly,

Thank you for your comments. Adding AC coupling cap is a possible solution, but it needs huge size. I still prefer to do it in active way. While the clock signal through AC coupling cap cannot be held, if my period is a little slow, like 500kHz, it may have troubles.
Thanks again.

Title: Re: How to generate the synchronized clock signals for two different grounds.
Post by loose-electron on Apr 22^nd, 2014, 3:43pm

1) create a differential current on the first device
2) terminate the differential current on the other device with a pair of resistors (or active loads)
3) recover the clock using a comparator attached to the termination loads

should get it done.

Title: Re: How to generate the synchronized clock signals for two different grounds.
Post by aaron_do on Apr 22^nd, 2014, 5:49pm

Hi,

Why don't you use a level-shifter to get ANA_2? The closest example I could find is this,

http://www.freepatentsonline.com/7102410-0-large.jpg

but its in a patent, so don't use it directly. Anyway the standard design works fine, just can't seem to find it. I think you need to take the outputs from PD1 and PD2, and remove 219, 221, 223, and 225 to get back the standard design. Or just search around for CMOS level shifter and you should find something...

regards,
Aaron

Title: Re: How to generate the synchronized clock signals for two different grounds.
Post by Jacki on Apr 23^rd, 2014, 3:18pm

loose-electron wrote on Apr 22^nd, 2014, 3:43pm:

Hello loose-electron,

Thank you very much for your advice, it is quite straight forward.

Title: Re: How to generate the synchronized clock signals for two different grounds.
Post by Jacki on Apr 23^rd, 2014, 3:26pm

aaron_do wrote on Apr 22^nd, 2014, 5:49pm:

Hello Aaron,

Thank you very much. I will think how to modify it to my application.

Title: Re: How to generate the synchronized clock signals for two different grounds.
Post by loose-electron on Apr 24^th, 2014, 4:29pm

Jacki wrote on Apr 23^rd, 2014, 3:18pm:

loose-electron wrote on Apr 22^nd, 2014, 3:43pm:

Hello loose-electron,

Thank you very much for your advice, it is quite straight forward.

Happy to help, you could also use an optical isolator if it is between chips