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Design >> Mixed-Signal Design >> How does this comparator work?
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Message started by Jacki on Apr 24^th, 2014, 5:07pm

Title: How does this comparator work?
Post by Jacki on Apr 24^th, 2014, 5:07pm

Hello,
I am try to design a SAR-ADC example, and I try to build a comparator first. The comparator I used is from the paper "A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC", the structure of the comparator and the testbench I used are shown below.
The comparator is differential, I use 900mV DC voltage at the negative input, at the positive input, I use the ramp voltage from 850mV to 950mV, 1mV per step. This testbench I used is for the offset test.
The problem is this comparator doesn't work. I cannot find any reason. I also try to reset the inputs, but still I cannot get the correct results.
Can anybody hint me some potential errors I did?
Thank you.

Title: Re: How does this comparator work?
Post by Jacki on Apr 24^th, 2014, 5:09pm

Here is the structure of comparator.

Title: Re: How does this comparator work?
Post by Jacki on Apr 24^th, 2014, 5:27pm

Jacki wrote on Apr 24^th, 2014, 5:09pm:

Here is the structure of comparator.

For this comparator, it looks like based on inverter, since the output of first stage is connected to the output second stage, a kind common mode voltage can be set for the inverter at the first stage.

Title: Re: How does this comparator work?
Post by aaron_do on Apr 24^th, 2014, 6:06pm

Hi,

I've been known to be wrong, but I think I see a major flaw with the comparator you posted and I if I'm right, I would steer clear of this design.

The problem is that the input has no common-mode rejection. Its pseudo-differential. So taking your example where Inn is connected to 900mV, how do you know what the threshold of the inverter is? The inverter connected to Inn might be permanently ON. So if Inn = Inp = 900mV, both inverters could be ON. The only way to get it to work would be to set the input common-mode of Inn and Inp equal to the threshold of the inverters, and that's an unreliable way to design a comparator IMO.

regards,
Aaron

Title: Re: How does this comparator work?
Post by Jacki on Apr 25^th, 2014, 2:29pm

Hello Aaron,

Thank you very much for your explanation. At the beginning I am also confused about the threshold voltage of this comparator. Since this paper is in JSSC, then I think it should work well for most of the cases. I will set the common mode voltage, and try it again. But the common mode voltage should vary as the process corners, do you think this comparator is sensitive to the process variation?
Thank you.
Jacki

Title: Re: How does this comparator work?
Post by aaron_do on Apr 26^th, 2014, 1:19am

You're welcome. Anyway just because its in JSSC doesn't mean its a good circuit. On the other hand, it might be suitable for the author's application. Bear in mind that its a 5-bit design whereas your SAR is presumably a lot higher...

regards,
Aaron

Title: Re: How does this comparator work?
Post by loose-electron on Apr 27^th, 2014, 2:21pm

As somebody who has been a reviewer for the IEEE JSSC - Just because it is there doe not make it a good design.

Suggest doing something with a differential pair amplifier structure.

Title: Re: How does this comparator work?
Post by RobG on May 21^st, 2014, 9:27am

It looks like the cross coupled inverters are preset with outp high. In order to change the output the signal from the input stage must be strong enough to flip the latch so it would need to be very large. That is probably why it isn't working. Normally cross coupled nands are used so both outputs start balanced high.

I don't like the comparators where the latch output is driven by the input stage because small offsets in the latch can prevent it from flipping. It is better to drive one of the gate or source inputs of a cross coupled nand.

As others have pointed out, these types of input stage topologies have poor common mode rejection, although I'm seeing a lot of them used. The CMR can be managed by using longer devices and the common mode input is normally controlled by the common mode output circuitry of the previous stage... Nonetheless, I'm old school and prefer to use a standard diff pair with high CMR that I know works rather than cut corners only to wonder if my corner cutting is why the part "almost" works. Don't risk the whole project to save 4 transistors...

And I agree with the others that say just because it is in JSSC doesn't mean you should use it. Most of the authors are students with no real world experience.

Title: Re: How does this comparator work?
Post by loose-electron on May 22^nd, 2014, 4:07pm

IEEE JSSC is a mixed bag of quality, some good and some bad.