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Design Languages >> Verilog-AMS >> verilog-A syntax for a capacitor or resistor
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Message started by bigball on Apr 30^th, 2014, 6:14pm

Title: verilog-A syntax for a capacitor or resistor
Post by bigball on Apr 30^th, 2014, 6:14pm

Hi:

Does VerilogA have the same syntax as verilog_AMS?

I'd like to add a capacitor and resistor to my verilogA modeling, is the following code correct? By the way, how do I add thermal noise to the resistor? Thanks.

inout a,b;
electrical a,b;
parameter real r=4K from (0:inf);
parameter real c1=200p from (0:inf);
parameter real c2=6p from (0:inf);
electrical int;

capacitor #(.c(c1)) C1(a, int);
capacitor #(.c(c2)) C2(a, b);
resistor #(.r(r)) R(int, b)

Title: Re: verilog-A syntax for a capacitor or resistor
Post by boe on May 8^th, 2014, 2:05am

bigball wrote on Apr 30^th, 2014, 6:14pm:

Yes, Verilog-A is a sub-set of Verilog-AMS. Did you try your code? What was the result? The noise modelling functions should be described in the documentation.
- B O E

Title: Re: verilog-A syntax for a capacitor or resistor
Post by Geoffrey_Coram on Jul 8^th, 2014, 7:23am

The syntax you've shown uses the Spice compatibility documented in Annex E of the Verilog-AMS LRM; that means, you are actually adding Spice capacitors and resistor, and the simulator should be including the thermal noise of the resistor, as it would for a resistor in its native netlist format.

You could write your own module for the resistor and use white_noise to add thermal noise.