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Modeling >> Behavioral Models >> DNL/INL Simulations for my ideal behavioral ADC model
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Message started by eternity on May 1^st, 2014, 2:10am

Title: DNL/INL Simulations for my ideal behavioral ADC model
Post by eternity on May 1^st, 2014, 2:10am

Hi,
I have been trying to plot DNL/INL for my ideal behavioral model of SAR ADC. I have my whole system (except the capacitor DAC block) implemented in Verilog-A.

I have added the blocks from ahdlLib of Spectre to compute INL and DNL. The results that I see after a looong simulation doesnt make any sense to me. So could any of you help me in guiding the right way to perceive these results.

Details: I am designing a 10 bit SAR ADC. So I have given the input ramp ranging from 0 to 1V in [1024*5*(1/sampling_rate)] seconds. I gave NO_OF_CONVS constant as (1024*5), NO_OF_CODES constant as 1024 in adc_dnl_10bit block that I customised from ahdlLib.

Issue-1: The result that I get as my DNL output is directly superimposing on my ramp input. The result says the maximum DNL is at code 1. I am sure the result is wrong and I dont know why at the moment. The digital output of my ADC is given as input to adc_dnl10bit block. Is it right or?

Issue-2: I am not able to write the result to the filename I mentioned in the adc_dnl_10bit verilogA file. The code syntax is out_file = $fopen( "%C:outp_dnl.dat" )

Eternity.

Title: Re: DNL/INL Simulations for my ideal behavioral ADC model
Post by Geoffrey_Coram on Jul 8^th, 2014, 7:39am

I don't think you've given us enough information to help you.

Should NO_OF_CONVS mean anything to us? Do we need to have access to adc_dnl_10bit from ahdlLib? Can you post any of your modules?

For issue=2, have you tried using $fopen of a simpler filename? That is, just "outp_dnl.dat" Is the problem with opening the file, or with writing to it? Perhaps %C doesn't work, or maybe ":" is a reserved character.

Title: Re: DNL/INL Simulations for my ideal behavioral ADC model
Post by weber8722 on Mar 1^st, 2015, 11:00am

Hi,

what may also help is not only using adc or dac from ahdllib, but also the ahdllib measurement blocks for inl and dnl. Very nice modules, also working with a ramp.

Bye Stephan