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Simulators >> AMS Simulators >> How to save digital signal in mixed-signal simulating using spectreVerilog
https://designers-guide.org/forum/YaBB.pl?num=1400080536

Message started by wendyyang100 on May 14^th, 2014, 8:15am

Title: How to save digital signal in mixed-signal simulating using spectreVerilog
Post by wendyyang100 on May 14^th, 2014, 8:15am

Hi all,

I am new to here, and I am doing some analog and mix-mode design now.

I try to save digital signals ( all the digital signal in the design, not just the output of digital part) in the verilog code as follows:
initial
begin
$dumpfile( "wave.vcd");
$dumpvars( 0, digital);
end

But I found the saved waveform only have initial value, all that after initialization don't exist.

The analog part works well, and the output of the digital part is right send to analog part. Thus, I guess the fault located in the saving.

How do you save the digital signals using verilog?
How to fix this problem?

Thank your for your patience~

Wendy

Title: Re: How to save digital signal in mixed-signal simulating using spectreVerilog
Post by wendyyang100 on May 18^th, 2014, 9:00pm

Please some body reply me how to view the internal digital signal when using spectreVerilog.
Thanks a lot.

Title: Re: How to save digital signal in mixed-signal simulating using spectreVerilog
Post by Geoffrey_Coram on Mar 26^th, 2015, 7:03am

Since your saving is done in an "initial" block, why are you surprised that you only get initial values?

Title: Re: How to save digital signal in mixed-signal simulating using spectreVerilog
Post by wendyyang100 on Mar 29^th, 2015, 10:10am

Hi! Thanks for your reply.

In my opinion, the initial block tells the simulator to start dump signals. Not just for the initial moment.

Could you please tell me how do you dump your results?

Thanks for your kind help. I was too happy to find an answer, and found I made a mistake when posting, so I modified this again...

Geoffrey_Coram wrote on Mar 26^th, 2015, 7:03am:

Since your saving is done in an "initial" block, why are you surprised that you only get initial values?

Title: Re: How to save digital signal in mixed-signal simulating using spectreVerilog
Post by Ken Kundert on Mar 30^th, 2015, 12:00pm

This can be tool specific. Tell us more about your situation.

-Ken