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Design Languages >> Verilog-AMS >> Simulation Speed in verilogams: Digital Context versus Analog Context
https://designers-guide.org/forum/YaBB.pl?num=1400577344

Message started by Zorro on May 20^th, 2014, 2:15am

Title: Simulation Speed in verilogams: Digital Context versus Analog Context
Post by Zorro on May 20^th, 2014, 2:15am

Dear Designer's Guide Team,

Let's assume that I have a verilogams module where I have to implement some functionality and I can do that either in the digital context or in the analog context. Which approach will simulate faster?
I understand that by using verilogams by default the digital and analog kernel will be used by default, so this is where my question arises.

I will try to explain with an example. I want to monitor an analog signal. I can do something like this using only the digital context:

always @( above(V(vdda_v)-(vdda_v_LoRange)) or above((vdda_v_HiRange)-V(vdda_v)) or // vdda_v rises above the low threshold or falls below the high threshold
above((vdda_v_LoRange-dv)-V(vdda_v)) or above(V(vdda_v)-(vdda_v_HiRange+dv)) // vdda_v rises above the high threshold or falls below the low threshold
) begin

if ( (V(vdda_v)>=vdda_v_LoRange) && (V(vdda_v)<=vdda_v_HiRange) ) begin
vdda_v_state = 1'b1;
vdda_v_flag = 1'b1;

end else begin
vdda_v_state = 1'b0;
if (vdda_v_flag==1'b1) begin
$fstrobe(output_file, "WARNING: V(vdda_v)=%gV is exceeding the defined safety ranges at time=%gus\n", V(vdda_v), $realtime);
end
end
end

I can also write the previous code in a very similar way in the analog context i.e. inside the analog begin... end block.

So, my questions are:

1. If I write my code only in the digital context, will the simulation run faster?

2. If there is no analog begin...end block inside the module, will this make the simulation run faster? Or, by default, because it is a verilogams module both analog and digital engines/kernel will be activated (by default) and there will be no difference in the simulation speed.

3. This question is more related to the approach or the way of writing the code. Which approach would be more recommended in terms of simulation speed? To use, if possible, only the digital context or it does not make any considerable difference?

Regards and thank you for your feedback!
Zorro

Title: Re: Simulation Speed in verilogams: Digital Context versus Analog Context
Post by Geoffrey_Coram on Jul 8^th, 2014, 7:53am

If there's no analog block, then I wouldn't expect the analog solver to be "activated" -- or at least, even if it is started up, it will be rarely called and/or take large timesteps.

Part of the answer to your question might depend on what sort of signals you are working with; your example was monitoring an analog signal, and it could be that it is more efficient to monitor that from an analog block, rather than having the simulator hand off values between analog and digital.