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Measurements >> Phase Noise and Jitter Measurements >> phase jitter simulation for case OSC + divider
https://designers-guide.org/forum/YaBB.pl?num=1401749242

Message started by tianyun1116 on Jun 2^nd, 2014, 3:47pm

Title: phase jitter simulation for case OSC + divider
Post by tianyun1116 on Jun 2^nd, 2014, 3:47pm

I was running PSS and PNOISE sim to test jitter performance of my oscillator, which is followed by a frequency divider. The output is from divider and the clock goes to ADC. ADC clock input is a threshold circuit, so I think only jitter performance is of concern. Noise type in PNOISE is PM jitter for driven circuit.

1. I played with PSS and PNOISE a while. And I found some results I can't explain. The clock is square wave, so I choose shooting but not harmonic PSS to calculate frequency. In my assumption the number of harmonic shouldn't be matter to PNOISE result, since I choosed shooting, but it turns out the result changed a lot once i modified the number of harmonic.

2. I also case about frequency and jitter result over temperature. I had chance to make test chip for my osc, and from lab, the jitter result increase with temperature, which match with my expectation, since white noise and flicker noise play a big role. but in simulation, the result doesn't match with my expectation. I can't see the trend of jitter perform with temp. But I also simulate OSC alone by using source noise type, the result did match, the integrated phase noise increase with temp. So for my case like autonomous OSC pluse a frequency divider, how should I set up PSS and PNOISE setting?

3. I don't know whether my setting is accurate enough, does anyone has any idea about this?

Thank you so much
Aaron

Title: Re: phase jitter simulation for case OSC + divider
Post by tianyun1116 on Jun 2^nd, 2014, 3:47pm

add Pnoise setting