The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> Sigma-Delta Decimation Filter: CIC
https://designers-guide.org/forum/YaBB.pl?num=1402666258

Message started by Christoforos on Jun 13^th, 2014, 6:30am

Title: Sigma-Delta Decimation Filter: CIC
Post by Christoforos on Jun 13^th, 2014, 6:30am

Hello everyone,

I have modelled a decimation filter after a Sigma-Delta converter in MATLAB. The passband frequency is 10 Hz and the downsampling ratio is 512. The decimation filter I am using is the Hogenauer CIC filter. The filter is stable up to and including the 3rd order. From 4th order it becomes unstable. Also, when I look at teh zplane the poles of the filter are just outside or the unit circle. Can someone help me to fix this?

Thank you

Title: Re: Sigma-Delta Decimation Filter: CIC
Post by Burt Harris on Aug 29^th, 2015, 6:04pm

I've been researching 4th order CIC filters as well. I found a really good article here where Richard Lyons explains CIC filters http://www.embedded.com/design/configurable-systems/4006446/Understanding-cascaded-integrator-comb-filters

He says Although recursive, happily CIC filters are guaranteed stable, linear-phase shown in Figure 4b, and have finite-length impulse responses. So, even without reviewing your model, I suggest the only problem might be that round off errors in Mathcad introduced small errors in the location of the poles and zeros. It seems intuitively reasonable to me that they must be stable given their time-series behavior.

Lyon's book, Understanding Digital Signal Processing, 2Ed, apparently contains more detailed description. Personally, after reading his very clear article, I'm ready got go buy a copy of his book.

Now, I'm interested in implementing a 4th order CIC filter for decimating input from a PDM digital Microphone using a low-density FPGA. Can anyone help express such a filter in Verilog, I'm a novice with this language?