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The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Accurate duty cycle for sampling clock in ADC https://designers-guide.org/forum/YaBB.pl?num=1402981671 Message started by aaron_do on Jun 16th, 2014, 10:07pm |
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Title: Accurate duty cycle for sampling clock in ADC Post by aaron_do on Jun 16th, 2014, 10:07pm Hi all, I need an accurate duty cycle for the sampling clock in my ADC. I was thinking to design a simple DLL based on a string of varactor-loaded inverters, a PFD, a charge-pump, and a single capacitor loop filter. I'm wondering if this is the typical approach or does anybody have any better ideas. I could just use a tunable delay line (string of inverters again), but then it would need to be calibrated. Any input is welcome. thanks, Aaron |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by raja.cedt on Jun 17th, 2014, 3:33am hi Aaron, I haven't designed any DCC for ADC but have done few for high speed clock duty cycle corrector. basically many people use analog loop, but I am not sure about DLL based. The basic idea would is low pass filter the clock so you would end up with dc level above or below vdd/2 based on your duty cycle now correct Duty cycle with current starved inverters until you see vdd/2 dc after low pass filter. However there is even simple idea with high pass filter. Please check fig 5 in the following pap. http://www.ece.tamu.edu/~spalermo/ecen689/2012_28Gbps_4tapffe_15tapdfe_xcvr_bulzacchelli_jssc.pdf Thanks, Raj. |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by aaron_do on Jun 17th, 2014, 5:41pm Hi Raj, thanks for the suggestion. Actually I had thought about something like that, but the only problem is that I also need a clock signal which goes low just before my main clock goes high again. Also, it honestly seems as complicated as a DLL :P I will keep your suggestions in mind and maybe think of some alternative. thanks, Aaron |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by loose-electron on Jun 20th, 2014, 7:51pm how many clock edges? what frequency? what alignment between edges? what accuracy? whats available as a reference clock source? define the question please |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by RobG on Jun 21st, 2014, 10:57am Why don't you create 2x the clock frequency and divide by two with a toggle flop? |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by raja.cedt on Jun 21st, 2014, 11:43am @RobG, Divide by 2 might be easy and low power at ADC clocking frequencies but don't you think 2X is difficult. Very options like 2X with XoR gate or is there any other method. I know this is very common at VCO level but I haven't seen any other places. Thanks, Raj. |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by RobG on Jun 21st, 2014, 12:03pm raja.cedt wrote on Jun 21st, 2014, 11:43am:
I'm guessing I'm missing something about your application that prevents you from using 2x frequency to begin with. I assume you know that you can divide by two with a flip flop like this:  What am I missing? |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by aaron_do on Jun 22nd, 2014, 7:56am Hi all, I'm trying to get a duty cycle of ~36%. When you mention divide by 2 I assume you're talking about getting 50% duty cycle? As for the number of clock edges, I also need one clock edge just before the end of one period, with no overlap. As this is just a test chip, right now the scheme I'm using is basically just using tunable delays and some logic to prevent overlap. I'm mainly wondering now what is the standard method for dealing with this? So is it common to see a delay-locked loop on an ADC chip? That seems like the best solution to me. thanks, Aaron |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by RobG on Jun 22nd, 2014, 10:23am aaron_do wrote on Jun 22nd, 2014, 7:56am:
Oh, wow, I knew I must be missing something. Yes, I was thinking you were after 50%. |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by loose-electron on Jun 24th, 2014, 3:08pm loose-electron wrote on Jun 20th, 2014, 7:51pm:
One more time... |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by aaron_do on Jun 24th, 2014, 6:22pm Hi loose-electron, Quote:
1) I need three clock edges. The first two form the sampling clock, and the last is to trigger an event. 2) 160 MHz. 40nm CMOS 3) alignment? Do you mean the spacing? The first two form a roughly 36% duty cycle (DC) clock. The last edge triggers just before the 36% DC clock. 4) Accuracy is not important (DC could be from 30% to 40% for example), but jitter should be around 1ps rms or less. 5) As this is a test chip, the clock source will be a signal generator. you know, despite not giving all of the information you asked for, I got some very useful answers. Raj. mentioned sensing the duty cycle, and RobG mentioned the use of dividers (although div 2 won't give the edges I need, div 3 or more might). I just need some general guidelines, and I'm intelligent enough to sort out what can and what can't be used in my system. Also, even if a method can't be used in my work, it may still be interesting to hear... regards, Aaron |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by loose-electron on Jun 26th, 2014, 5:51pm aaron_do wrote on Jun 24th, 2014, 6:22pm:
When shooting at a target, the probability of success is much higher when you know what the target is and where it is placed. Better yet, if you can see the target, so much the better. You can use a DLL to subdivide the clock (or generate defined delays) to get what you want. Other options are possible as well. |
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Title: Re: Accurate duty cycle for sampling clock in ADC Post by aaron_do on Jun 26th, 2014, 8:43pm Quote:
So the question is whether I provided a visible enough target for the level of accuracy that I required...... thanks anyways for the help, Aaron |
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