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Design Languages >> Verilog-AMS >> Using Parameters in VerilogA and VerilogAMS
https://designers-guide.org/forum/YaBB.pl?num=1403683591

Message started by Srinivas_BS on Jun 25^th, 2014, 1:06am

Title: Using Parameters in VerilogA and VerilogAMS
Post by Srinivas_BS on Jun 25^th, 2014, 1:06am

Hi All,

I have a lot of parameters in my verilogams code. Is there any way in which I can associate each port of a module with a parameter. By this I mean, can we create a provision where, a user instantiates a symbol (created from verilogams code) in the schematic, and as he makes connection to a port, clicks by its side and edits the parameter associated with that port. Such a provision would make my model look neat.

If someone could throw light on handling modeling problems involving a lot of parameters, it would be of great help.

Thank you.

Title: Re: Using Parameters in VerilogA and VerilogAMS
Post by boe on Jun 25^th, 2014, 10:08am

Hi Srinivas_BS,

Quote:

... can we create a provision where, a user instantiates a symbol (created from verilogams code) in the schematic ...

Strictly, this is a question about the schematic entry tool you use (whatever that is)...
I don't know any V-A/A-AMS support for this.
I would suggest to reconsider the code (maybe there is a different approach that needs fewer params) or consider using a V/V-A/V-AMS netlist to instantiate your model.
- B O E

Title: Re: Using Parameters in VerilogA and VerilogAMS
Post by Srinivas_BS on Jun 25^th, 2014, 9:08pm

Hi boe,

Thanks for your feedback. I am using Cadence tools, Virtuoso schematic editor. I want to model a resistor ladder, where I want to manually specify the value of resistors during instantiation. And the number of resistors in the chain itself gets passed as a parameter.

Title: Re: Using Parameters in VerilogA and VerilogAMS
Post by boe on Jun 26^th, 2014, 9:08am

Hi Srinivas_BS,
you should be able to find a practical implementation for instantiating your resistor ladder model in another block written in V/V-A/V-AMS, but unfortunately, I don't know any practical solution to this problem with Virtuoso Schematic editor.
- B O E

Title: Re: Using Parameters in VerilogA and VerilogAMS
Post by Geoffrey_Coram on Jul 8^th, 2014, 7:45am

Srinivas_BS wrote on Jun 25^th, 2014, 9:08pm:

... I want to manually specify the value of resistors during instantiation. And the number of resistors in the chain itself gets passed as a parameter.

This would seem to require a symbol that dynamically resizes itself to have the required number of ports. I think you have to figure that out in your schematic editor; Verilog-AMS can't help you with the symbol.