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Design >> Mixed-Signal Design >> Stability analysis of linearized vco
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Message started by pmathew on Jun 26^th, 2014, 3:04pm

Title: Stability analysis of linearized vco
Post by pmathew on Jun 26^th, 2014, 3:04pm

I am trying to checkout the linearized vco from

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1052757&tag=1

I am wondering how to test the stability of this loop if it needs to be done in cadence (transistor level) . since the loop has a frequency to voltage and the a voltage to frequency converter will pac work in this situation . I tried simulating a simple current starved ring followed by a switched cap resistor in open loop with pss pac but dont see any gain from input to switch capacitor output . I dont know whether i am doing anything wrong .

Thanks
mathew