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Simulators >> Circuit Simulators >> How to deal with simulation with too many pins?
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Message started by wayne_luo on Jul 1^st, 2014, 8:28pm

Title: How to deal with simulation with too many pins?
Post by wayne_luo on Jul 1^st, 2014, 8:28pm

Hi everyone,

I have a question when I simulated a simple adder by cadence virtuoso. I've designed a 64-bit adder and would like to make a simulation. But it seems too boring when I do so because there are almost 200 pins. That is to say if I just use vpulse (NCSU_Analog_Parts -> Voltage_Sources -> vpulse) in this process, I need more than 100 voltage sources in my design that will be boring and time consuming. Are there some other kind of sources that can be used in this situation or some other method?

Thanks a lot!

Title: Re: How to deal with simulation with too many pins?
Post by Ken Kundert on Jul 1^st, 2014, 8:47pm

Use Verilog-AMS for the testbench. Once you use Verilog-AMS for this you will never go back to using a schematic.

-Ken

Title: Re: How to deal with simulation with too many pins?
Post by wayne_luo on Jul 1^st, 2014, 10:48pm

Thanks for your response, Ken.

I know the Verilog-AMS and it should be a good choice, but I just wonder if I can do this simulation by cadence spectre. Maybe I can extract the netlist of the model from the schematic and simulate it by coding manually. It seems a boring work too.

-Wayne

Title: Re: How to deal with simulation with too many pins?
Post by Ken Kundert on Jul 2^nd, 2014, 12:55am

You would use AMS Designer. Write a Verilog-AMS testbench and instantiate the schematic. You can then fully exercise the adder with a few lines of code. You can even make the testbench fully self checking.

-Ken