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Design >> Mixed-Signal Design >> how to build EFT
https://designers-guide.org/forum/YaBB.pl?num=1404697820

Message started by bsaqycx on Jul 6^th, 2014, 6:50pm

Title: how to build EFT
Post by bsaqycx on Jul 6^th, 2014, 6:50pm

Dear all,

I've no idea how to build EFT test modeling. EFT means that the high voltage pulse(+-4000 V, lasting for ~100 ns, 100kHz) is introduced to the input AC source and the system output should not go down to 0 V.What's more, the introduced pulse could affect every pin of the chip because of the small size of the whole system.
For now, it's very difficult to predict the performance on this issue without proper testbench. Now I'm looking forward to some advice from you. Thanks in advance.

Title: Re: how to build EFT
Post by loose-electron on Jul 7^th, 2014, 5:38pm

http://electronicdesign.com/power/know-your-regulations-you-design-medical-electronics

http://electronicdesign.com/power/protect-your-fortress-esd

give the above 2 a read. the EFT test is common to medical devices

Title: Re: how to build EFT
Post by bsaqycx on Jul 7^th, 2014, 9:26pm

Thank you very much for your help!
I'm wondering how to build such EFT pulses generator for simulation. I've no idea about the storage capacitor should be used.

Title: Re: how to build EFT
Post by loose-electron on Jul 8^th, 2014, 12:06pm

In the real world instrument companies sell EFT generators.

For simulation, you should be able do a PWL generator to get an approximate signal.