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Design >> Mixed-Signal Design >> Reading INL and DNL Plots
https://designers-guide.org/forum/YaBB.pl?num=1406122929

Message started by jockeymonto on Jul 23^rd, 2014, 6:42am

Title: Reading INL and DNL Plots
Post by jockeymonto on Jul 23^rd, 2014, 6:42am

Hi ,

I attaching INL and DNL plots of my designed SAR ADC. It is a 12 bit differential monotonically switched bridge cap ADC. The INL and DNL plots are pretty bad and I need to know where exactly is something wrong in my SAR ADC. If someone can comment on how to relate the INL and DNL plots to the circuit level implementation, then plz comment.

Title: Re: Reading INL and DNL Plots
Post by carlgrace on Jul 23^rd, 2014, 10:27am

It's an art that you get a feel for through doing a lot of design.

Looking at your plot I would guess you have a segmented DAC in your SAR. Is that correct? It seems like the large DNL spikes are at regular intervals, that indicates a big mismatch between the coarse and fine sections of your DAC.

Also, the structure in your INL is unusual. I suspect your switches aren't settling. What is the time constant of your switches and caps compared to the clock period?

Title: Re: Reading INL and DNL Plots
Post by eternity on Jul 23^rd, 2014, 1:49pm

Adding to carlgrace's comment, whats your unit cap value..probably thats making your INL and DNL plots look ugly.

Also one more query, how many samples you consider per code level for your MATLAB INL/DNL simulation(slow ramp or slow sine waveform) to compute INL/DNL (if at all you are exporting the output data outside your CAD tool). The less number of samples you take per code level can also lead to this scenario.

One more thought, your accuracy of capacitor values matter here as well, as it determines bascially the linearity of your ADC

Eternity

Title: Re: Reading INL and DNL Plots
Post by carlgrace on Jul 23^rd, 2014, 3:41pm

Eternity makes a good point. How many samples did you take? Is it a ramp or a sine wave input?

If it is a ramp, the DNL resolution is 1 LSB / average number of samples per bin. So if you want your DNL measurement accurate to 0.1 LSB you need 10 samples per code of 40000 samples.

If you're using a sine it's more complicated.

Even if you have "perfect" matching in your simulation there is still parasitic capacitance from your switches and comparator input. This causes an effective dynamic mismatch if the unit cap is small compared to the parasitics (as Eternity indicated).

Title: Re: Reading INL and DNL Plots
Post by jockeymonto on Jul 24^th, 2014, 1:03am

Thankyou carlgrace and eternity for your comments. I took 4096 points using a ramp input signal for taking these INL and DNL plots. After doing some more experiments I strongly agree with carlgrace point that I need to take some more data points. I hope this would result in better plots. Because these 4096 data points did not result in an ideal ‘staricase’ structure, instead it was more like a combination of ramp + staircase.
I am using 65nm CMOS node with a unit cap of 20fF. It’s vertical natural cap…..MIM cap.
Yes I am using a segmented DAC. I have two 6 bit DACs separated by a bridging cap. One DAC computes 6 MSBs while the other one computes 6 LSBs. I have no calibration in my ADC.
Yes the MSB and LSB DACs were mismatched so I added extra 100fF cap on the LSB DAC such that the ADC output resulted almost exactly as Vin/Vref over the entire input range.
I did work out the settling time issues on this ADC several weeks ago and I don’t think this is an issue now. My clock frequency is 200kHz with a period of 5us which I have set to be far greater than the settling time of my TG switches.

Title: Re: Reading INL and DNL Plots
Post by loose-electron on Jul 24^th, 2014, 7:09pm

looks like you got some calibration and alignment circuits to add in. This is hopefully still at the simulation level.

Title: Re: Reading INL and DNL Plots
Post by eternity on Jul 25^th, 2014, 2:38am

@loose-electron, may be its a diversion from the main topic of this thread
Just curious to know what you meant by alignment circuits..can you educate me with this?

Thanks
Eternity

Title: Re: Reading INL and DNL Plots
Post by loose-electron on Jul 25^th, 2014, 10:11am

you have a device that the offsets/gains and stage to stage matching are showing problems.

Since you have not shown us any schematics we can't comment that well on what to fix.

If this is silicon and not simulation you got a lot of redesign to do.

http://electronicdesign.com/products/simulation-vs-silicon-avoid-costly-mistakes-accurate-models

Read the above, read the details of what I say there.

Title: Re: Reading INL and DNL Plots
Post by jockeymonto on Jul 26^th, 2014, 5:49am

Hi loose-electron, Thanks for your input. I read your article...if one takes care of all the suggestions you have mentioned, he can come up with a rigorous design. I will look into all the things you mentioned during my design. And BTW i am still at schematics level simulations stage.

I have a question about mismatch. Since I am using DAC capacitive array in my SAR ADC, I have multiple unit capacitors connected in parallel. Is it true that connecting devices of same size (like unit cap in DAC array) in parallel reduces the amount of mismatch? I have no calibration circuit till now but i have run MC simulations several times on my ADC but the resulting Vin/Vref for different runs at room temperature varies around 4-5 LSBs (0.2mV) about its nominal value. (I am using an ideal comparator right now, so the major mismatch source is the DAC capacitive array)

Title: Re: Reading INL and DNL Plots
Post by loose-electron on Jul 26^th, 2014, 6:24pm

jockeymonto wrote on Jul 26^th, 2014, 5:49am:

As a general rule, scaling the geometry up in size or increasing the numbers of devices in a matched array does improve matching.

However, beyond a certain degree the matching improvement reduce. For size scaling (the resistor body goes from 2um to 6um lets say) the matching accuracy will not be a linear curve.

Get the matching data for your foundry process.