The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> RF Design >> LNA |Z22| reduction in RLCK
https://designers-guide.org/forum/YaBB.pl?num=1406614980

Message started by VINAY RAO on Jul 28^th, 2014, 11:22pm

Title: LNA |Z22| reduction in RLCK
Post by VINAY RAO on Jul 28^th, 2014, 11:22pm

Hello all,
I am designing LNA with every element on-chip in 65nm technology (refer figure). With only RC extraction, |Z22|=1.1K. However, when RLCK extraction is done for 2.14GHz, |Z22| is drastically getting reduced to 390 Ohms though Ld, Ls and Lg are placed far from each other. Due to that LNA gain is becoming worse. Is this the problem with RLCK extraction ? How come parasitic inductance and its mutual inductance can degrade output impedance by such a value? Can you suggest how degradation of |Z22| can be avoided?

Title: Re: LNA |Z22| reduction in RLCK
Post by aaron_do on Jul 29^th, 2014, 12:36am

Hi,

maybe your resonant frequency has shifted? Did you sweep frequency? Also, why are you looking at |Z22|? It seems Re{Y22} is more relevant in your case. If there's really a layout issue, then its difficult to see the problem without looking at the layout. However, you can assume every long line is a parasitic inductor and also see where the parasitic capacitors would be and see if there's likely to be any impedance transformation. Or maybe its a software issue and there's a double extraction going on or something like that. Just gonna have to slowly debug.

Aaron

Title: Re: LNA |Z22| reduction in RLCK
Post by raja.cedt on Jul 29^th, 2014, 2:23am

Hi,
Did you consider paracitic inductance between M2 drain and Ld, I guess that resonance frequency has gone down as aaron_do said. Please try to plot o/p impedance and see the shift in centre frequency...

Thanks,
Raj.

Title: Re: LNA |Z22| reduction in RLCK
Post by tm123 on Jul 29^th, 2014, 6:31am

Vinay Rao,

Perhaps you can create a layout view with the inductors moved up one level in the hierarchy. This way you can extract the circuit with everything but the inductors and see if coupling between inductors is really your problem.

Tim

Title: Re: LNA |Z22| reduction in RLCK
Post by VINAY RAO on Jul 29^th, 2014, 8:34am

Hello Aron and Raja,
Thanks for your reply. Resonant frequency is perfect. I have attached the figure where I have increased ld from 12nH to 18nH. And |Z22| increased from 390 to 640. I took the details from the extraction.
From M2 drain to Vout: 54pH + 39fF
From Vout to Ld: 263pH+26fF (Here I purposefully increased length from Vout to Ld to increase impedance)
At Vdd line: 225pH+20fF

Whether these values degrading so severely? So how can I find out impedance transformation with this?

Ps: I have attached layout in the reply below.

Regards,
Vinay

Title: Re: LNA |Z22| reduction in RLCK
Post by VINAY RAO on Jul 29^th, 2014, 8:35am

Hello tm,
Thanks for your reply. I moved away Lg and Ld but it didn't help much. Moreover, I am taking same current direction for both Lg and Ld. If that then that have to increase overall inductance through mutual inductance? I have attached layout too here. Left one is LG, top one is LD and bottom one is LS.

Regards,
Vinay

Title: Re: LNA |Z22| reduction in RLCK
Post by aaron_do on Jul 29^th, 2014, 6:46pm

Hi,

a few comments.

1) when you increased Ld, your Rout increased. This suggests that maybe your inductor Q is the bottleneck. Try using a higher-Q inductor. I originally thought it might be feedback, but you mentioned moving Ld away didn't help...

2) The reason I suggested using Y-parameters instead of Z-parameters is because your output network is better modeled by parallel RLC. With Y-parameters, the real part will be less frequency dependent.

3) Based on the direction of the metal turns for Ld, the long line from OUT to Ld is decreasing your overall inductance, not increasing it. Unless I'm viewing it wrongly, it appears that the currents are flowing in opposite directions.

4) Are those blue lines ground shields? I assume that you're not showing us some of the layers right? I would do a study to see how effective those ground shields are.

5) Your final design is going to have a non-negligible inductance from VDD to ground because they are far away from each other. Eventually they need to get to a point where they can couple nicely together. Just FYI...

6) The connections between your inductor shields are forming a rather large short-circuit loop. This should be avoided as any current coupling to the loop will burn up in the loop's resistance. Its a good way to de-Q inductors. In your case, it may not have too much effect (would have to simulate). For grounding separate blocks, star connections are best if possible, but if not, I would use thick grounding lines to keep the impedance low.

7) I've never actually used the Assura inductance extraction. Is that what you're using? I'm not sure how accurate it is. You could try comparing it with something like ADS momentum...

regards,
Aaron

edit:
Just noticed that those blue lines surrounding your inductors seem to be unbroken. If that's true then see point 6.

Title: Re: LNA |Z22| reduction in RLCK
Post by VINAY RAO on Jul 29^th, 2014, 9:27pm

Hello Aaron,
Thank you again. :)
1> I rechecked it. Moving away Ld or Ls further gave error like “FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit: ”. It seems to be a different issue so I posted in cadence forum.

I also tried to move away Lg to left side and it increased |Z22| from 640 to around 720 Ohms. There might be an issue with mutual inductance but how it can be reduced without further wasting area?
( I used highest possible Q for Ld that is around 8. )

2> Regarding Y-parameters, only analysis becomes easier but it will not differ further result anyway. My only issue is LNA gain is degraded due to reduction in output impedance.

3>Increasing OUT to Ld actually increased |Z22|.

4>Yes. Those are ground shields where M1 is used for that.

5>I am not cleared enough. Why good coupling is required between VDD and ground. For VDD I used M8 and for GND I used M1.

6>I don't have any idea how star connections can be made for this case and can you give any reference to study about those? But ground shields are not shorted as there is short gap in between.

7>Yes. I am using Assura QRC. Would the CALIBRE help in-terms of accuracy?

Regards,
Vinay.

Title: Re: LNA |Z22| reduction in RLCK
Post by aaron_do on Jul 29^th, 2014, 10:50pm

Hi Vinay,

I think you need to be careful here. Simply moving the inductor in one direction or another may reduce one effect and increase another. As much as possible you should try and isolate the effects. I suggest the following.

1) split up your layout into a few sections. The Ld network, the Lg network, the Ls network, and the transistors.

2) extract the individual networks one by one and gradually replace the ideal components with extracted ones.

3) finally add all components into one layout. This will reveal any coupling.

Regarding your other questions.

1) To get higher inductor Q, you need to design the inductors yourself.

2) Up to you. To me there are four possibilities.
a) There is some impedance transformation. But looking at the trace lengths and the sizes of your inductors, I doubt this would have such a great effect. If I remember correctly, impedance transformation wouldn't change the "available" power at the output, so you can look at that to verify.
b) Your inductors are being de-Q'd. Make sure there are no large closed metal loops as these will kill your inductor Q. Especially in the ground shields.
c) There is some feedback. Coupling between your inductors could result in feedback which would reduce your gain.
d) There is a problem with your extraction. Try using an EM simulator for the inductors and traces.

3) I made a slight mistake here. Increasing that line would indeed increase Ld, but not so effectively, as the mutual inductance between Ld and the OUT-Ld trace appears to be negative in your case. This is not good because it lowers the Q of the inductors. If Ld turns in the opposite direction, you should be able to get even higher inductance and better Q. But because the trace is small, the effect may also be small.

4) Make sure there are no closed loops in the ground shields. I'm sure you've heard of eddy currents...

5) VDD and GND are both considered to be AC ground. At AC they should be the same net, and so its good to have strong coupling between them. That's the general rule anyway...

6) There definitely appears to be a loop in between the three inductors formed by the connections between the ground shields. I cannot stress enough how amazing this book is,

http://www.amazon.com/Signal-Power-Integrity-Simplified-2nd/dp/0132349795/ref=la_B001H9VNIG_1_1?s=books&ie=UTF8&qid=1406698826&sr=1-1

its by Eric Bogatin and its called Signal and Power Integrity Simplified. It will answer all of your questions for you and everybody will think you're half man, half amazing :D

7) I'm not really sure about the difference between Calibre and Assura. For L and K extraction I've only used EM simulators.

cheers,
Aaron

Title: Re: LNA |Z22| reduction in RLCK
Post by VINAY RAO on Aug 4^th, 2014, 8:05am

Hi Aaron,

I have used pcell from UMC, it says EM effects are embedded in inductors' model. And in docs, inductor response shows accurate matching with this model. Is it necessary still to use EM simulators separately for those inductors? Or is it ok if only interconnections are taken care of in normal simulators like assura or calibre?

3> I flipped the inductor and so now out line and Ld branch currents are in same direction. It definitely helped but improvement is insignificant.

4> How one can make strong coupling between VDD and GND? Any tips for it ?

5> I shorted every instructor's ground shield with each other. But in individual inductor, surrounding ground shields are not shorted. There is a little gap in between.

Regards,
Vinay.

Title: Re: LNA |Z22| reduction in RLCK
Post by aaron_do on Aug 4^th, 2014, 6:59pm

Hi Vinay,

For your circuit, the inductors are much larger than the trace inductance. So trace inductance is unlikely to have any effect. So it may not be necessary to use EM simulators for the inductors. Regarding your points,

3) You mentioned something about deliberately extending that wire to increase inductance. If you don't want it to affect the performance then you shouldn't do this. On the other hand, if you want to increase the inductance, it seems to me that its better to keep the wire close to the inductor, or simply use an inductor with an extra half turn.

4) You could route VDD on top of GND, and keep the bonding wires adjacent to each other. In your case they are on opposite sides of the chip (see my figure). The effect may not be so great as you will have a ground plane on the PCB, and you are using very large inductors anyway. But its something you should consider.

5) See my figure. As I mentioned before, by joining all of the ground shields, you may be creating a closed loop. The size depends on where the break is in your ground shields. This kind of closed loop can de-Q your inductors. I'm just guessing there's a loop here as it seems so from the figure.

Another thing I'm not so sure about is whether the ground shields really help. Maybe somebody else could weigh in. I think the idea is that if there's any substrate noise from other blocks, it will couple to the ground shield instead of the inductors. But in your case, the same ground is used to bias your transistor bodies. It may be that the ground shields need their own bondwire. I'm not really sure...

cheers,
Aaron

regards,
Aaron

Title: Re: LNA |Z22| reduction in RLCK
Post by totowo on Nov 16^th, 2014, 5:56pm

1. Obviously the routing of Ld (from VDD to Ld, from Ld to OUT)is quite long to decrese your Q.
Why not swap the inductor pin? VDD above and OUT below. so that the routing is much shorter and the series resistance is much lower.

2. Another important issus is the gate of cascode device should be well AC ground, a long trace from VDD is not a good choice, you'd better add bypass cap near the gate to provide a really low impedance at cascode gate......You could check the effect of non-ideal bias in simulation, by adding a resistor in the cascode gate.

3. BTW, Z22 or (1/Y22) is not the same as ZM2. it's not an issue in cascode lna design, but you should keep it in your mind.

VINAY RAO wrote on Jul 29^th, 2014, 8:34am: