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Design >> Mixed-Signal Design >> SAR and Pipelining Architectures
https://designers-guide.org/forum/YaBB.pl?num=1407010225

Message started by Mir on Aug 2^nd, 2014, 1:10pm

Title: SAR and Pipelining Architectures
Post by Mir on Aug 2^nd, 2014, 1:10pm

I need to finalize whether i should go for SAR or Pipelining ADC design....

can u suggest me ....

Specifications required..

Resolution bit:- 14
Sampling rate:- 1Msps
Mux:- 4:1..

with xplaination plz

Title: Re: SAR and Pipelining Architectures
Post by carlgrace on Aug 4^th, 2014, 9:59am

14 bit is pushing it for a pipelined ADC unless you want to calibrate or you don't really need 14-bit ENOB and your application is more SNDR oriented.

That said, getting a 14-bit SAR to work well above 1 MS/s is non-trivial to say the least, but it depends on your process.

You really need to give more information for to make an informed choice. What process are you using? What are the key specs? What is the signal bandwidth? etc etc etc

Title: Re: SAR and Pipelining Architectures
Post by loose-electron on Aug 4^th, 2014, 2:27pm

At that rate and resolution you should probably consider oversampling architecture Delta Sigma methods.

Agreed more info is needed however to give good advice.

Title: Re: SAR and Pipelining Architectures
Post by aaron_do on Aug 4^th, 2014, 6:29pm

Hi,

check out this work.

Kapusta, R. ; Analog Devices, Inc, et. Al., "A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS" JSSC vol. 48, no.12.

It seems that if you have a fast enough process, a SAR is doable. Also, if the design is doable using a SAR, then go with a SAR, but if the speed requirement can't be met, then pipeline. Perhaps the experts could weigh in on the pros and cons of pipeline versus SAR as I'm also very interested. My understanding:

FOR SAR
1) Only 1 linear node.
2) Lower power due to no high gain amplifiers.
3) More scalable and benefits more from technology scaling.
4) Easier to do with just one low-voltage supply.

FOR Pipelined
1) Faster.
2) In SAR, internal clock rate is N times higher than pipelined ADC.

Anybody care to add to that?

cheers,
Aaron

Title: Re: SAR and Pipelining Architectures
Post by Mir on Aug 5^th, 2014, 1:42am

Other specifications are:

Input voltage +/- 10V
Mux 4:1
INL +/- 2 LSB
DNL +/- 1LSB
SNR 70 dB

Title: Re: SAR and Pipelining Architectures
Post by aaron_do on Aug 5^th, 2014, 3:55am

Hi,

Input voltage +/- 10V.

Is that a typo? What process are you using? What do you mean by 4:1 MUX?

Aaron

Title: Re: SAR and Pipelining Architectures
Post by Mir on Aug 5^th, 2014, 8:19am

THE MUX WILL BE USED AT THE INPUT....MORE THAN 2 INPUTS

Title: Re: SAR and Pipelining Architectures
Post by loose-electron on Aug 5^th, 2014, 10:16am

aaron_do wrote on Aug 5^th, 2014, 3:55am:

Hi,

Input voltage +/- 10V.

Is that a typo? What process are you using? What do you mean by 4:1 MUX?

Aaron

20V? Voltage division at the input with R-poly will get that done.

Foundry process is the big question here - if it is submicron CMOS at that sample rate I would go Sigma-Delta,

If it is old 1.2u CMOS SAR might be the path to take.

Very slow sampling rate so I do not see a need to do a pipeline.

Title: Re: SAR and Pipelining Architectures
Post by carlgrace on Aug 5^th, 2014, 5:43pm

loose-electron wrote on Aug 5^th, 2014, 10:16am:

aaron_do wrote on Aug 5^th, 2014, 3:55am:

Hi,

Input voltage +/- 10V.

Is that a typo? What process are you using? What do you mean by 4:1 MUX?

Aaron

Since the OP is using a 4-1 MUX in the front of the ADC, the real sampling rate is 4 MS/s.

I've got to disagree with loose-electron a bit here in that I think a 14-bit SAR at 4 MS/s is a very challenging design, especially in an old process. A pipeline at 4 MS/s would be pretty easy.

Also, interfacing a sigma-delta to a multiplexed input can be challenging depending on the characteristics of your signal source and what you're trying to achieve. So beware.

Your specs are in kind of a weird spot... not obvious which way to go since several approaches could work here.

Title: Re: SAR and Pipelining Architectures
Post by Mir on Aug 6^th, 2014, 1:11am

i am really thankful for ua sugestions!!

i have to use AMS 180 nm Tech.

and it has to be designed for data acquisition system

Title: Re: SAR and Pipelining Architectures
Post by carlgrace on Aug 6^th, 2014, 11:20am

If it were me doing the design I would probably go with the pipeline. Since your SNR requirement is somewhat challenging, and because 4 MS/s is a piece of cake in 180nm, I would consider oversampling. If you run the converter at 16 MS/s, say, and take 4 samples of each input and average them, you'll improve your SNR by 6 dB. Then you won't have to worry as much about kT/C and OTA noise.

I actually did just this is an instrumentation SOC design a few years ago, accept it was in 65nm and much faster.

Please note that my advice is probably biased because I've designed a lot of Pipelined ADCs so I'm much more familiar with their capabilities than other types of ADCs.

Have fun designing!

Title: Re: SAR and Pipelining Architectures
Post by loose-electron on Aug 6^th, 2014, 12:40pm

OK, so 0.18, 14 bit, 4MHz sampling.

I would go through the literature and look at sigma delta, pipelines and SAR methods.

If power is a big issue the pipeline will eat a lot of power, sigma delta not as much.

Research papers next, If I may suggest.

Title: Re: SAR and Pipelining Architectures
Post by RobG on Aug 6^th, 2014, 1:59pm

A delta-sigma won't be easy because there are multiple inputs. You will have to reset it each time to flush the buffers and integrators, which makes it an incremental where you have to oversample it quite a bit more to get the same resolution... I think a 3rd order will require 4*OSR samples... see Quiquempoix, "A Low Power 22-bit Incremental ADC," JSSC, July 2006. You might be able to pull it off with a high order one.

I just went through this on a bid for a 32 input 18-bit ADC. I'm still not sure how/if I'm going to make that ADC happen but was thinking of a pipelined SAR with the cap mismatch calibrated out. I think that will work well for you too. Look at some of the newer pipelined SAR papers to see how they are done. They can be pretty power efficient.

Title: Re: SAR and Pipelining Architectures
Post by carlgrace on Aug 6^th, 2014, 2:17pm

I think the confusion is the OP hasn't ever said what the real specs are. What is important?

Power? Go with a SAR or pipelined-SAR like Rob suggests.

Time? Go with a Pipelined ADC. Maybe a 3.5-bit first stage and then 1.5-bit stages after that. Since you're going slow, you don't have to worry about cap size and power. Use the 3.3 V devices, make big, double-cascode op amps and don't worry too much.

OP doesn't seem to be an expert so going for something simple is the way to go.

Title: Re: SAR and Pipelining Architectures
Post by loose-electron on Aug 7^th, 2014, 7:49pm

Good point on the sigma delta and the front end sampling. Agreed that may be an issue.

Title: Re: SAR and Pipelining Architectures
Post by SNIKE on Aug 28^th, 2014, 10:38pm

My 2 cents:

1) Delta sigma : Cannot be used. Because of 4 Inputs , we loose noise shaping [every time we reset, memory is lost] .
2)Pipeline ADC : Do you care about latency? If yes Pipeline is overkill.
use Cyclic or SAR instead.
3)Flash : Cannot be done. Need Fancy/expensive folding techniques.
4)Slope techniques: May be slow, requires huge oversampling. Good for multiplexing, as you can have separate registers and filters in digital domain. Again speed is issue.

Historically SAR has been published with higher ENOB. I am inclined towards SAR.

Title: Re: SAR and Pipelining Architectures
Post by eternity on Sep 2^nd, 2014, 3:53am

Is the confusion regarding mentioned Vdd resolved?
10V for 180 nm process?
Highly unlikely as the oxide breakdown occurs way before you reach 10 V.

Eternity

Title: Re: SAR and Pipelining Architectures
Post by loose-electron on Sep 3^rd, 2014, 3:00pm

eternity wrote on Sep 2^nd, 2014, 3:53am:

Is the confusion regarding mentioned Vdd resolved?
10V for 180 nm process?
Highly unlikely as the oxide breakdown occurs way before you reach 10 V.

Eternity

resistive voltage division before you hit a transistor