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Design Languages >> Verilog-AMS >> OR Model
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Message started by bki on Aug 22^nd, 2014, 4:37am

Title: OR Model
Post by bki on Aug 22^nd, 2014, 4:37am

Hi,

i have a problem with the VerilogA OR Model. I always get errors.
Can someone help to modify it?

This is the Code:

`include "constants.vams"
`include "disciplines.vams"

module V_or(in,out);
input [0:1] in;
output out;
voltage [0:1] in;
voltage out;

parameter real size = 2 from [2:inf),
vout_high = 5,
vout_low = 0 from (-inf:vout_high),
vth = 1.4,
tdelay = 1n from [0:inf),
trise = 1n from [0:inf),
tfall = 1n from [0:inf);
integer in_state[0:1];
integer out_state;
integer j;
real vout;
genvar i;

analog begin
@(initial_step) begin
for(j=0;j<2;j=j+1) begin
in_state[j]=0;
end
end

for (i=0;i<2;i=i+1) begin
@(cross(V(in[i]) - vth)) begin
in_state[i] = V(in[i]) > vth;
end
end
out_state = 0;
for(j=0;j<2;j=j+1) begin
if (in_state[i]) begin
out_state = 1;
end

if (out_state) begin
vout = vout_high;
end

else begin
vout = vout_low;
end
end
end

Thank you!!!!

Title: Re: OR Model
Post by boe on Aug 22^nd, 2014, 9:55am

bki,
see this post.
Also, please provide codeproperly formatted and enclosed in [ code ] <add your code here> [ /code ] (without the spaces).
- B O E

Title: Re: OR Model
Post by Ken Kundert on Aug 22^nd, 2014, 10:31am

http://www.designers-guide.org/VerilogAMS/functional-blocks/gates/gates.va