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Message started by raja.cedt on Aug 26th, 2014, 9:17am

Title: BGR PSRR
Post by raja.cedt on Aug 26th, 2014, 9:17am

Dear all,
I have been looking at a paper with high psrr band gap located at

http://sms.unipv.it/~franco/ConferenceProc/188.pdf

Basically I didn't get the main point here to improve PSRR. I have attached fig 3 here. basically at low frequency low takes hence good psrr, but at high frequency(near to bandwidth) Vc2 will be coupled vdd through Cgs3, but here the same thing got enhanced by Mn42. With the above argument I didn't understand what is the need of MN41,MN42, infract this additional stage will introduce systemic error.

Can any one please explain in-briefly how this is improving psrr?

Thanks,
Raj.


Title: Re: BGR PSRR
Post by carlgrace on Aug 26th, 2014, 10:54am

Interesting paper!

What's going on here is the power supply noise is being canceled to first order (similar to those noise-canceling LNAs).

Think of it this way:

If there is some noise on VDD, it will modulate the current through M2 and M3.  This will modulate the voltage on V+ and V- because the current is flowing through Q2 and Q1.  Now, the op amp will then adjust its output accordingly.  

VC2 is the subtraction of a diode drop and the opamp output (and is nominally the correct bias point for M2 and M3).  Since MN41 sees the same VGS modulation as M2, the current through MN41 will have the same power supply noise on it as M2.  So, to first order, this noise is canceled on VC2.

This obviously will work only at frequencies much lower than the frequency of operation of the devices and op amp.  However, it seems to work well at 1 kHz.

I surprised I haven't seen this paper as I have designed several bandgaps.  I wonder why it isn't a more standard design.

Title: Re: BGR PSRR
Post by raja.cedt on Aug 26th, 2014, 1:04pm

Hi,
I know bram nauta noise cancelation technique, but some I couldn't understand this in that way. In any -ve feedback we can find some kind of subtraction.

Coming to the circuit one thing I didn't understand. To have better power supply behaviour some one has to adjust gate of M2 to deltavdd(1+1/(Gm3*R03)) to cancel properly. For the frequency below Loop-Bandwidth opamp does this job properly, this is the reason why we have very good psrr in any feedback ckt(around 50dB), but the main question is how to get better PSRR around the BW, since no one is there to change M3 gate (except Cgs3). You are also concluding that this techniques also work below BW then improving opamp and this technique doesn't have any difference. What do you say?

Same idea has been implemented for LDO also   here..http://ee.sharif.edu/~elec3/Regulator/0759hoon.pdf

Thanks,
Raj.

Title: Re: BGR PSRR
Post by carlgrace on Aug 26th, 2014, 1:26pm

If I understand you correctly I think we agree that this only works within the GBW of the op amp.  The PSRR is only shown up to 1 MHz.  I suspect the PSRR would not be improved beyond the GBW of the op amp, but the paper does not specify it.

I think if you improve the GBW of the op amp you will increase this PSRR improvement to higher frequencies.

Title: Re: BGR PSRR
Post by sushan on Aug 26th, 2014, 9:23pm

I remember using this circuit some years ago, when I was having the opamp second stage as NMOS CS. And the paper too talks about having NMOS CS as the second stage where the relative cancellation of Vdd PSRR is bit bad. And if there is sufficient separation between your Amp's BW and your Cgs correcting for Vdd PSRR then this would be the fastest loop to correct it.

Title: Re: BGR PSRR
Post by RobG on Aug 27th, 2014, 8:56am

I'm feeling dense and don't see it... what terms need to match to get cancellation?

The Miller configuration of the baseline design would give bad rejection at high frequency, so I think his cancellation scheme would also improve the AC rejection over the miller opamp design, but you could probably do better than a miller.

I prefer to compensate the loop with a big cap between Vdd and Vc1 as it gives better AC power supply rejection but that doesn't work well if you already have two stages in from of Vc1.

I also like tying the ends of R2 and R3 together gives better noise performance.

I'm not sure the improvement could be adapted to either of the above methods I prefer. I'm a little worried about what has to match to get the improvement. Biasing a PMOS with an NMOS isn't such a great idea either. He has four poles in his loop... lots of things that would prevent me from using the design directly, but perhaps the concept could be adapted to better topologies. But my dense brain needs to understand what cancels first.

Title: Re: BGR PSRR
Post by aaron_do on Aug 27th, 2014, 8:02pm

Hi,


without the author's additional circuitry, the PSRR would be limited by the bandwidth of the Op-Amp. The additional circuitry tracks the source voltage of the PMOS, i.e. the power supply, and applies it to the gate voltage of the PMOS. With VGS = 0 in the PMOS, no current will flow (i.e. PSRR is good).

I believe that this tracking circuit (MN41 and MN42) is intended to work independently of the Op-Amp, and so is not limited by the op-amp's bandwidth. At high frequency (beyond the op-amp GBW), assume the Op-Amp is cut-off and the AC gate voltage of MN42 is zero. Then the AC voltage at Vc2 is determined by the gain through MN41 (equal to 1) from the power supply. i.e. the PSRR can be boosted well beyond the GBW of the op-amp. It is no substitute for the op-amp because as you all pointed out, the op-amp provides significantly better DC PSRR.

Actually I think normally to get high frequency PSRR, you would add a cap from VC2 to VDD, but in this case it would degrade the op-amp's GBW.


regards,
Aaron

EDIT: I think RobG was pretty much thinking along the same lines. Its not so much a cancellation as having the gate voltage track the source. I agree that having the NMOS bias the PMOS wouldn't necessarily be a good match, but I think the only purpose is to have an AC gain of 1 for the tracking circuit, so in that respect, the NMOS are faster than PMOS.

Title: Re: BGR PSRR
Post by raja.cedt on Aug 28th, 2014, 3:06am

@robg,
what do you mean by I also like tying the ends of R2 and R3 together gives better noise performance.
.Biasing a PMOS with an NMOS isn't such a great idea either, means systematic offset or any thing else in your mind?

@arron..I agree with you , this additional stage or a cap between vc1 and vdd are doing same job..

In general I found many people are bit reluctant to use this idea. Can you people suggest me any good idea for LDO to get midband psrr better than let's say 20dB

Thanks,
Raj.


Title: Re: BGR PSRR
Post by RobG on Aug 28th, 2014, 6:45am


raja.cedt wrote on Aug 28th, 2014, 3:06am:
@robg,
what do you mean by I also like tying the ends of R2 and R3 together gives better noise performance.
.Biasing a PMOS with an NMOS isn't such a great idea either, means systematic offset or any thing else in your mind?

@arron..I agree with you , this additional stage or a cap between vc1 and vdd are doing same job..

In general I found many people are bit reluctant to use this idea. Can you people suggest me any good idea for LDO to get midband psrr better than let's say 20dB


Bear in mind I'm reluctant only because I haven't had time to figure out how it works. With his idea the opamp output now sees Vgs of MN41, which is removed once from Vdd variations. I'm not sure that the benefit isn't just from doing that. Plus it hasn't been too much of an issue for me to get 100dB of DC rejection so I'm not included to solve a problem I've never had ;). However, it might be a fine idea.

Regarding tying the resistors together - M2 and M3 are used to create equal current, but they contribute thermal noise. The noise can be reduced by making their Vgs-Vt larger, but you run out of headroom. It turns out the optimum way to use this headroom is to use identical resistors - they are already dropping ~600mV which is enough. The down side is that it uses more area. I'm sure you have seen the result before:


My concern with using MN41 to bias M2 and M3 is over corners. The current in MN42 will need to change a lot to provide the proper bias for M2 and M3. This may affect the stability of the loop. It is already on the edge since he has two poles in the opamp and another in M2 and M3.

For good AC power supply rejection I would compensate the opamp with a cap and resistor in series between VC2 and VDD. (The resistor adds a zero to cancel the first pole). This will help AC rejection assuming the cap between VC2 and VSS is small. This won't work well with a two-stage opamp so instead of the miller opamp I would use a folded cascode with a PMOS input pair.

[edit... sorry for all the edits after my original posts. I seem to be making more typos and confusing statements these days.]

Title: Re: BGR PSRR
Post by loose-electron on Aug 28th, 2014, 1:10pm

BAD circuit architecture!  :(

Anybody that uses active noise cancellation on a DC reference signal has probably not characterized the circuit in the real world.

Thing is, this method will work within the limitations (both BW and Phase!) of the feedback system.

At least on paper.

Truth is noise in a mixed signal environment is wide BW and not well defined.

The V-ref in this case is high impedance. So, put some capacitance to ground and be done with it. :)

If you have low frequency noise on the power, then it's time to go fix your power supply, not try to bandage the bandgap reference with a feedback system.  :D

Title: Re: BGR PSRR
Post by carlgrace on Aug 29th, 2014, 7:57am


loose-electron wrote on Aug 28th, 2014, 1:10pm:
BAD circuit architecture!  :(

Anybody that uses active noise cancellation on a DC reference signal has probably not characterized the circuit in the real world.

Thing is, this method will work within the limitations (both BW and Phase!) of the feedback system.

At least on paper.

Truth is noise in a mixed signal environment is wide BW and not well defined.

The V-ref in this case is high impedance. So, put some capacitance to ground and be done with it. :)

If you have low frequency noise on the power, then it's time to go fix your power supply, not try to bandage the bandgap reference with a feedback system.  :D


That makes sense.  I'm a pretty conservative designer so all three of the bandgap references I've designed used the standard textbook architecture because it was good enough.  I think this is a good lesson for younger designers.... only innovate or use a tricky circuit when you must.

Title: Re: BGR PSRR
Post by loose-electron on Aug 29th, 2014, 1:47pm

keep it simple whenever possible.

Title: Re: BGR PSRR
Post by aaron_do on Aug 29th, 2014, 5:18pm

I think for this circuit, loose-electron is right, but more generally speaking, I think the idea of tying the current mirror's gate to its source by active means has merit and could find application in some circuits.


Aaron

Title: Re: BGR PSRR
Post by loose-electron on Aug 31st, 2014, 4:08pm

in some circuits for sure, but not here

Title: Re: BGR PSRR
Post by analog_rf on Sep 15th, 2014, 7:15am

This particular "add on" consisting of an nmos driver and a diode connected pmos load is called a substractor as already pointed out. Although i have not used it in case of a bandgap ,i have used this for a high psrr LDO and it works great. Think of it this way: The opamp path for restoring the output is slow, the direct path provided by the gate of diode connected transistor provides a very fast path for replicating the ripples on the supply, on the pmos diode connected tran and hence the bandgap or ldo pmos transistors.Hence ac psrr would be better. for the bandgap in question,what is the PSRR target?

Title: Re: BGR PSRR
Post by RobG on Sep 15th, 2014, 7:38am

I still haven't had a chance to look in depth at this - it could be a great idea - but wouldn't you get the same effect if you used a PMOS output stage with Miller compensation driving M2 and M3? (Or better, from the gate of M2/M3 to Vdd) Perhaps with an LDO you would be load compensated.

Title: Re: BGR PSRR
Post by analog_rf on Sep 15th, 2014, 8:59am

As mentioned already ,haven't used this in case of Bandgap. For BG PSRR i would prefer using a Folded cascode dominant pole compensated and also add small load cap of maybe 10pf at output will give good psrr no's @ac.

Title: Re: BGR PSRR
Post by analog_rf on Sep 15th, 2014, 9:14am


RobG wrote on Sep 15th, 2014, 7:38am:
I still haven't had a chance to look in depth at this - it could be a great idea - but wouldn't you get the same effect if you used a PMOS output stage with Miller compensation driving M2 and M3? (Or better, from the gate of M2/M3 to Vdd) Perhaps with an LDO you would be load compensated.



Miller would be a killer for ac PSRR, since dominant pole would be internal and adding more cap would cause the internal pole to be pushed  further inside for stb(you could still use cap to supply,but will not be better than fc opamp).

Title: Re: BGR PSRR
Post by RobG on Sep 15th, 2014, 2:16pm


analog_rf wrote on Sep 15th, 2014, 9:14am:
Miller would be a killer for ac PSRR, since dominant pole would be internal and adding more cap would cause the internal pole to be pushed  further inside for stb(you could still use cap to supply,but will not be better than fc opamp).

Miller is what they are using now, except they are using an NMOS mirror so it is referenced to the bottom rail which will make PSRR bad because the output device is basically diode connected at AC. That is why I as thinking the shielding of the Miller "diode" from the gate of M2/M3 was the real advantage.

The weather is too nice for me to do the math right now :).


Title: Re: BGR PSRR
Post by loose-electron on Sep 16th, 2014, 3:58pm

generally your dominant pole in the control loop is going to be the output capacitor on the bandgap voltage. it may not seem elegant to some but its worked pretty well for many years, and if the output drive is high impedance (not a source follower) it generally will not be terribly big in size.

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