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Design >> High-Power Design >> Variable duty cycle clock generation
https://designers-guide.org/forum/YaBB.pl?num=1409932590

Message started by rf_1 on Sep 5^th, 2014, 8:56am

Title: Variable duty cycle clock generation
Post by rf_1 on Sep 5^th, 2014, 8:56am

Hi,

I am trying to do a "Verilog - A " model of a block which takes in a control voltage (duty cycle = d ) and a 50% duty cycle clock. as input. The output of this block is a clock with duty cycle 'd'.
I am not able to figure out how to go ahead with this problem.

I have looked into the following post
http://www.designers-guide.org/Forum/YaBB.pl?num=1138941612/15

Please advise

Thanks

(

Title: Re: Variable duty cycle clock generation
Post by loose-electron on Oct 20^th, 2014, 4:39pm

integrate the square wave - gives you a triangle wave

use the duty cycle value to set a comparison level.

switch states when the two signals equal in value.