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Design Languages >> Verilog-AMS >> Getting information about convergence of internal nodes
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Message started by Prasad Sarangapani on Sep 6^th, 2014, 7:55am

Title: Getting information about convergence of internal nodes
Post by Prasad Sarangapani on Sep 6^th, 2014, 7:55am

I am currently trying to simulate a device with Verilog-A which has two current sources in series between supply and ground. I was wondering whether it is possible to get information about the time taken for Spectre to find a converged voltage for the internal node. Also, how do I get total time taken by Spectre to simulate a Verilog-A module. Is it time that I see in the logfile ?

Title: Re: Getting information about convergence of internal nodes
Post by Geoffrey_Coram on Nov 13^th, 2014, 10:33am

I don't think any simulator will give you that sort of information -- like you can't ask a simulator to tell you how much time it spent evaluating BSIM4 models versus diodes in a regular Spice-like netlist.

I'm assuming you have other things in your circuit, so that the total simulation time is different from the time to simulate just your Verilog-A module.