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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> verilog-A dependent source NOT converge https://designers-guide.org/forum/YaBB.pl?num=1411221053 Message started by ywguo on Sep 20th, 2014, 6:50am |
Title: verilog-A dependent source NOT converge Post by ywguo on Sep 20th, 2014, 6:50am Hi Guys, I wrote one voltage controlled voltage source with verilog-A, which is used in a transient analysis of one buck model. The spectre simulator could not get initial point for transient analysis. The VCVS code is shown below. Code:
After I replaced it with a spectre VCVS, the buck model works. The spectre VCVS is shown below. Code:
What's wrong with my verilog-A code? How do I improve it? Thanks in advance. Yawei |
Title: Re: verilog-A dependent source NOT converge Post by Ken Kundert on Sep 21st, 2014, 8:11am Get rid of the initial step code. You are contributing the same thing to the output twice on the initial step. That creates an impulse at t=0 that is probably the source of you convergence issues. -Ken |
Title: Re: verilog-A dependent source NOT converge Post by Geoffrey_Coram on Sep 23rd, 2014, 2:23pm I'm also a little concerned about continuity at the breakpoints: V(out) <+ (V(in)>0.9) ? 0.9 : (V(in)<0.1) ? 0.1 : V(in)/vm; At V(in) = 0.9 plus a bit, the output is 0.9 At V(in) = 0.9 minus a bit, the output is V(in)/vm = 0.9/4 = 0.225 I don't think that's what the VCVS does. |
Title: Re: verilog-A dependent source NOT converge Post by boe on Sep 24th, 2014, 2:06am Geoffrey_Coram wrote on Sep 23rd, 2014, 2:23pm:
- B O E |
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