The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> special file names in Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1411791979

Message started by sutapanaki on Sep 26^th, 2014, 9:26pm

Title: special file names in Verilog-A
Post by sutapanaki on Sep 26^th, 2014, 9:26pm

Hi,

I want to run Monte-Carlo simulations, say 100 iterations and I want to record some data into a file with a name specific for each MC iteration. How can I do this in verilogA? Is there a way to append to the file name for example the time the simulation completes, or some other identifier specific to the MC iteration?
Thanks

Title: Re: special file names in Verilog-A
Post by Geoffrey_Coram on Nov 13^th, 2014, 10:30am

I don't recall that this is supported directly by the language; you should check with customer support for your simulator to see if they have special % codes for the analysis that you can use in Verilog-A, or if you can use them in a netlist to specify the output file as a parameter to your Verilog-A model.