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Design Languages >> Verilog-AMS >> mixing spice and VerilogA
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Message started by jmith on Sep 29^th, 2014, 9:10am

Title: mixing spice and VerilogA
Post by jmith on Sep 29^th, 2014, 9:10am

I'm looking for a simple example which contains a spice subcircuit and this subcircuit is referenced from a VerilogA model. My question is: how this spice file read from the VerilogA model, through an include file? Or there is no include file and the spice model found in an other way? Or there is a .lib command in the VerilogA model file?

Title: Re: mixing spice and VerilogA
Post by boe on Sep 30^th, 2014, 1:48am

Jmith,
you instantiate the subcircuit in Verilog-A. If it is in the Spice netlist your tool should use it.
- B O E

Title: Re: mixing spice and VerilogA
Post by jmith on Sep 30^th, 2014, 4:24am

From the Verilog-AMS Language Reference Manual

Code:

`include "disciplines.va"
`include "constants.va"

module diffPair (c1, b1, e, b2, c2);
electrical c1, b1, e, b2, c2;

vertNPN Q1 (c1, b1, e);
vertNPN Q2 (.c(c2), .b(b2), .e(e));
endmodule

Where vertNPN is a spice model line. I assume this code is can not compile. How to fix this code?

Title: Re: mixing spice and VerilogA
Post by boe on Sep 30^th, 2014, 9:28am

Jmith,

Quote:

... I assume this code is can not compile.

Why not? The tools I have available compile it.
Of course, it won't simulate unless you give an implementation for vertNPN.
- B O E

Title: Re: mixing spice and VerilogA
Post by jmith on Sep 30^th, 2014, 10:29am

It means in the VerilogA source file not needed to reference any Spice library?

Title: Re: mixing spice and VerilogA
Post by boe on Oct 1^st, 2014, 1:51am

jmith wrote on Sep 30^th, 2014, 10:29am:

It means in the VerilogA source file not needed to reference any Spice library?

Verilog-X does not need any definition of sub-cells to compile. Of course, the sub-cells need to be present for the simulation, though.
- B O E