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Design Languages >> Verilog-AMS >> fixed time step in Verilog-A?
https://designers-guide.org/forum/YaBB.pl?num=1412664633

Message started by fgcsk on Oct 6^th, 2014, 11:50pm

Title: fixed time step in Verilog-A?
Post by fgcsk on Oct 6^th, 2014, 11:50pm

Is there any way to have a fixed time step in Verilog-A?
I know $bound_step can limit the time step to a certain amount, but it does not guarantee the time step is fixed if I understand correctly.

Actually I just want to implement something like this:
Y = Y + dYdt*timestep

I know Y=idt(dYdt, 0) can do it, but at some events I also need to directly modify Y, and idt() is an analog operator that is not allowed to do so.
Any suggestions?

Title: Re: fixed time step in Verilog-A?
Post by Geoffrey_Coram on Nov 13^th, 2014, 10:22am

There is a reset argument to idt() that allows you to set the output to zero; can you use that?

What you're asking for is a little tricky; what happens when the simulator fails to converge at a timepoint (due to nonlinearities in other parts of the circuit) and backs up to take a smaller time step? Will it know how to back out the direct modifications you made to Y ?

Title: Re: fixed time step in Verilog-A?
Post by fgcsk on Nov 22^nd, 2014, 11:54pm

Thanks for explaining why there is no fixed time step.
The reset argument of idt cannot help, and I've already come up with a way to solve this problem, which is to separate the total Y into two variables.
One is the idt(), and the other one is the modification.