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Simulators >> AMS Simulators >> Multiple Supply in a chip
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Message started by Aj1234 on Oct 8^th, 2014, 10:40am

Title: Multiple Supply in a chip
Post by Aj1234 on Oct 8^th, 2014, 10:40am

Hi,

I had a question in Verilog AMS setup. Do you know how to use connect modules in a chip which have multiple supply domains. I know one method in which we write using ie card in amsd block in ams control file:

amsd {

… ie vsup=1.8
ie vsup=3.3 cell=dig_buf
}

Does anyone know how to do this in cadence gui? Is there any tutorial?

Thanks,
AJ

Title: Re: Multiple Supply in a chip
Post by boe on Oct 13^th, 2014, 3:44am

Aj1234,
in ADE you use Setup->Connect Rules.
For tutorials, a quick search in Sourcelink should give you several hits, e.g. "Virtuoso AMS Designer Environment Tutorials" and "Running the Virtuoso AMS Designer Simulator from the Analog Design Environment and the Hierarchy Editor".
- B O E