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https://designers-guide.org/forum/YaBB.pl Other CAD Tools >> Physical Verification, Extraction and Analysis >> Spectre_simulator : Post layout verification problem https://designers-guide.org/forum/YaBB.pl?num=1412917030 Message started by ghegde on Oct 9th, 2014, 9:57pm |
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Title: Spectre_simulator : Post layout verification problem Post by ghegde on Oct 9th, 2014, 9:57pm Hello, I am facing a problem while dong a post layout simulation of a simple inverter chain.I ran a transient analysis on current through voltage supply node(minus terminal) with an intention to know the current flowing through the circuit at different instant of time. Unfortunately Spectre complains that "Analysis `tran' was terminated prematurely due to an error."I am not able to understand what this error is and how to resolve it. Also there are errors like "ERROR (CMI-2049): I0.rvdd!_438 of Inv_Chain: Value of `leff' should be greater than zero.".What it means?? I have pasted the last few lines of out put log and attached Test bench circuit. Please note that there is no error reported for transient analysis for input signal and out signal. Any help to understand this issue or to resolve is greatly appreciated. Thanks in advance, ERROR (CMI-2049): I0.rvdd!_494 of Inv_Chain: Value of `leff' should be greater than zero. ERROR (CMI-2049): I0.rvdd!_495 of Inv_Chain: Value of `leff' should be greater than zero. ERROR (CMI-2049): I0.rvdd!_496 of Inv_Chain: Value of `leff' should be greater than zero. ERROR (CMI-2049): I0.rvdd!_497 of Inv_Chain: Value of `leff' should be greater than zero. Notice from spectre. 336 notices suppressed. 70 warnings suppressed. Time for parsing: CPU = 29.995 ms, elapsed = 37.5192 ms. Time accumulated: CPU = 552.915 ms, elapsed = 610.33 ms. Peak resident memory used = 61.6 Mbytes. ************************************************* Transient Analysis `tran': time = (0 s -> 100 ns) ************************************************* Notice from spectre during IC analysis, during transient analysis `tran'. Bad pivoting is found during DC analysis. Option dc_pivot_check=yes is recommended for possible improvement of convergence. DC simulation time: CPU = 29.996 ms, elapsed = 29.5141 ms. Important parameter values: start = 0 s outputstart = 0 s stop = 100 ns step = 100 ps maxstep = 1 ns ic = all useprevic = no skipdc = no reltol = 10e-06 abstol(V) = 1 uV abstol(I) = 1 pA temp = 27 C tnom = 27 C tempeffects = all errpreset = conservative method = gear2only lteratio = 10 relref = alllocal cmin = 0 F gmin = 1 pS Output and IC/nodeset summary: save 1 tran: time = 2.507 ns (2.51 %), step = 18.71 ps (18.7 m%) tran: time = 7.897 ns (7.9 %), step = 498.6 ps (499 m%) tran: time = 12.5 ns (12.5 %), step = 43.5 ps (43.5 m%) tran: time = 17.59 ns (17.6 %), step = 238.2 ps (238 m%) tran: time = 22.52 ns (22.5 %), step = 24.45 ps (24.5 m%) tran: time = 27.59 ns (27.6 %), step = 382.1 ps (382 m%) tran: time = 32.52 ns (32.5 %), step = 36.47 ps (36.5 m%) tran: time = 37.72 ns (37.7 %), step = 263.5 ps (264 m%) tran: time = 42.52 ns (42.5 %), step = 24.46 ps (24.5 m%) tran: time = 47.59 ns (47.6 %), step = 382.2 ps (382 m%) tran: time = 52.52 ns (52.5 %), step = 36.47 ps (36.5 m%) tran: time = 57.72 ns (57.7 %), step = 263.5 ps (264 m%) tran: time = 62.52 ns (62.5 %), step = 24.46 ps (24.5 m%) tran: time = 67.59 ns (67.6 %), step = 382.2 ps (382 m%) tran: time = 72.52 ns (72.5 %), step = 36.47 ps (36.5 m%) tran: time = 77.72 ns (77.7 %), step = 263.5 ps (264 m%) tran: time = 82.52 ns (82.5 %), step = 24.46 ps (24.5 m%) tran: time = 87.59 ns (87.6 %), step = 382.2 ps (382 m%) tran: time = 92.52 ns (92.5 %), step = 36.47 ps (36.5 m%) tran: time = 97.72 ns (97.7 %), step = 263.5 ps (264 m%) Number of accepted tran steps = 3590 Initial condition solution time: CPU = 29.996 ms, elapsed = 29.5751 ms. Intrinsic tran analysis time: CPU = 8.5757 s, elapsed = 8.58898 s. Analysis `tran' was terminated prematurely due to an error. finalTimeOP: writing operating point information to rawfile. designParamVals: writing netlist parameters to rawfile. primitives: writing primitives to rawfile. subckts: writing subcircuits to rawfile. Aggregate audit (11:38:04 AM, Fri Oct 10, 2014): Time used: CPU = 9.22 s, elapsed = 12.6 s, util. = 73.3%. Time spent in licensing: elapsed = 52.8 ms. Peak memory used = 65 Mbytes. Simulation started at: 11:37:52 AM, Fri Oct 10, 2014, ended at: 11:38:04 AM, Fri Oct 10, 2014, with elapsed time (wall clock): 12.6 s. spectre completes with 995 errors, 5 warnings, and 14 notices. |
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Title: Re: Spectre_simulator : Post layout verification problem Post by boe on Oct 13th, 2014, 3:28am ghegde wrote on Oct 9th, 2014, 9:57pm:
Quote:
Here the simulation runs. - B O E |
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Title: Re: Spectre_simulator : Post layout verification problem Post by sheldon on Oct 17th, 2014, 6:39am ghegde, `leff' is less than zero means that the effective channel length of a device is less than zero. The most likely cause is either you are using too short a gate length or you are using a low voltage device in a high voltage domain. Remember that channel length is modulated by drain depletion region. Sheldon |
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Title: Re: Spectre_simulator : Post layout verification problem Post by ghegde on Oct 21st, 2014, 2:30am boe wrote on Oct 13th, 2014, 3:28am:
Hi Boe, Thanks for the reply.May I know what additional information I can provide to better understand this problem?Also did you mean that simulation completed successfully? Thanks, |
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Title: Re: Spectre_simulator : Post layout verification problem Post by ghegde on Oct 21st, 2014, 2:36am sheldon wrote on Oct 17th, 2014, 6:39am:
Thanks Seldon for the help. The channel length of the device were 0.35um. Can you please elaborate a little your statement "you are using a low voltage device in a high voltage domain" for my better understanding? Thanks again, |
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Title: Re: Spectre_simulator : Post layout verification problem Post by sheldon on Dec 11th, 2014, 7:06am ghegde, If a high voltage is applied to a low voltage device, then the depletion region of the drain can reduce the channel length and potentially cause an "effective" negative channel length. Sheldon |
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Title: Re: Spectre_simulator : Post layout verification problem Post by ghegde on Dec 11th, 2014, 7:14am sheldon wrote on Dec 11th, 2014, 7:06am:
Thanks Sheldon. |
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