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Design >> High-Power Design >> PMOS Open drain: Lateral MOSFET vs Vertical MOSFET
https://designers-guide.org/forum/YaBB.pl?num=1413400564

Message started by jsaenznoval on Oct 15^th, 2014, 12:16pm

Title: PMOS Open drain: Lateral MOSFET vs Vertical MOSFET
Post by jsaenznoval on Oct 15^th, 2014, 12:16pm

Hi everyone,

I'm designing a 18V supply PMOS open drain switch and I want to choose adequately my PMOS pass transistor. I have two strong candidates:

pmmc -> 20V symmetrical HV PMOS Ron(@Vg=-5V)=73kOhm*um
ped2 -> 35V lateral p-DMOS Ron (@Vg=-5V) =57kOhm*um

In terms of layout I think that symmetrical devices are more area optimized. Additionally, ped2 has a lower resistance than pmmc. However, as far as I can see on the Internet, it is widely used lateral p-mos. Can anyone help me with the disadvantages and advantages of both transistors?
What device should I choose?

Title: Re: PMOS Open drain: Lateral MOSFET vs Vertical MOSFET
Post by loose-electron on Oct 20^th, 2014, 4:37pm

could you better explain what you are doing?
this is a discrete transistor correct?

Title: Re: PMOS Open drain: Lateral MOSFET vs Vertical MOSFET
Post by jsaenznoval on Nov 3^rd, 2014, 7:23am

Hi Jerry,

This open drain switch is to be integrated so it won't be implemented using discrete transistors. My question comes from the fact that lateral MOSFET occupies more area than vertical counterparts in the process that I'm using. Additionally, the vertical MOSFET layout is symmetric.
I want to know the differences between a lateral and vertical MOSFET and which I should be selected for my application, which is basically and on/off open-drain switch with a 1024ms pulse duration. From my point of view, I can perfectly use a vertical MOS because due application uses low frequency and switching performance doesn't matter.
Thanks!

What is your opinion?

Title: Re: PMOS Open drain: Lateral MOSFET vs Vertical MOSFET
Post by loose-electron on Nov 6^th, 2014, 4:07pm

need to know a lot more about the foundry process being used.

frequently NMOS switches get implemented with fancy gate control voltage boosting circuits because the NMOS devices have better high current characteristics.