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Design >> Mixed-Signal Design >> Loop bandwidth of PLL
https://designers-guide.org/forum/YaBB.pl?num=1413960963

Message started by J_im on Oct 21^st, 2014, 11:56pm

Title: Loop bandwidth of PLL
Post by J_im on Oct 21^st, 2014, 11:56pm

Is there any measurement technique to measure the actual loop bandwidth of a PLL module. I am asking about how to calculate it by using any formula. Please advice. Thanks

Title: Re: Loop bandwidth of PLL
Post by loose-electron on Oct 27^th, 2014, 1:33am

measure in the lab or determine from simulation?

you can do 2 different things in the lab - characterize the step response (step in phase/frequency and watch the loop respond) or characterize the response to a FM signal.

Title: Re: Loop bandwidth of PLL
Post by raja.cedt on Oct 27^th, 2014, 3:52am

1. I modulate the refclk phase at various offset frequencies (e.g. 50kHz to 20MHz) and measure the height of the resulting spurs on the spectrum analyzer. I define the height of the spur at the lowest modulation frequency as the 0dB point on the closed-loop transfer function H(s) and then generate the rest of H(s) by subtracting the height of the other spurs from this base value. This yields accurate measurement of the bandwidth (-3dB) but sometimes does not allow us to accurately measure peaking for well-overdamped PLLs (e.g. peaking < 0.5dB). The problem with peaking is that it can be difficult to accurately determine the 0dB point to within a few tenths of a dB. Note that you want to enable averaging on the spectrum analyzer to lower its noise floor(this was written by Dennis from AMD in a personal conversation with me).
2. Simple bot not accurate: measure VCO open loop phase noise and PLL closed loop noise and see where they crossing each other.

Thanks,
Raj.