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Design >> Analog Design >> Redundancy vs Calibration
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Message started by Lissa on Oct 29^th, 2014, 7:35am

Title: Redundancy vs Calibration
Post by Lissa on Oct 29^th, 2014, 7:35am

Hi all,

I am working on a 12 bit segmented SAR ADC. I need to if know calibration is used to cater for the device mismatch and process variations of DAC array while redundancy is used to recover from wrong comparator errors ? Can redundancy also be used for mitigating ADC errors coming from device mismatch?

Title: Re: Redundancy vs Calibration
Post by carlgrace on Oct 29^th, 2014, 2:56pm

Hello Lissa,

Redundancy is a way of making the ADC resistant to errors. It is a distinct concept from calibration. Either one (or often both) can be used to desensitize the circuit to device mismatch and process variation. Whether you use one or both depends on your specs and what errors you expect.

Redundancy is a hot topic in SAR design right now. You can get away without calibration in some cases if you add additional redundant cycles. You can think of this as a "time-domain" version of the well know hardware redundancy in pipelined ADCs. It is harder to get away without calibration if you add redundant hardware because then your radix can change and you must know the radix precisely (to the 1/2 lsb level ,at least).

Here is an excellent review paper that discusses these concepts and gives a lot of good references for you to read.

http://www.eurasip.org/Proceedings/Ext/SampTA2013/papers/p556-murmann.pdf

Title: Re: Redundancy vs Calibration
Post by Lissa on Oct 30^th, 2014, 12:40am

Thanks Carlgrace. I have read certain papers on SAR ADCs with redundancy but one thing that I am not able to figure out is how people decide where to implement redundancy (I mean for 12 bit ADC, some one may go with a redundant bit after 4 bits than another one after 4 bits......). During initial cycles of SAR conversion the comparator sees a large differential input (typically) which must narrow down to zero (ideally) by the end of SAR scheme. Should we not deduce from here that ADC is more likely to generate errors during the LSB cycles of SAR scheme and so redundancy must be implemented in the LSB bits instead of MSB bits?

Title: Re: Redundancy vs Calibration
Post by RobG on Oct 31^st, 2014, 8:01am

I'm working that problem right now with a 12b. The ADC is much easier to calibrate digitally if you use redundancy since you can force the ADC to take two paths and then apply digital correction to make the two paths give the same result.

Redundancy is awesome :D. For example, doing a 12 bit conversion with 15 comparisons can (if done correctly) allow very large errors for all but the last two comparisons. Therefore,
1) Your reference doesn't have to settle completely,
2) Your comparator can be very noisy and simple (i.e. fast latch), and
3) Offset differences between stages isn't important so you can use a fast latch for each of the stage

But remember these don't apply to your last two comparisons - they need a low noise comparator.

In addition, cap mismatches can be on the order of 25%, but they do have to be accounted for digitally, whereas the other errors require no digital correction.

Unfortunately, I haven't found many detailed papers to help me. This MIT Thesis was helpful, but I didn't think he did a good job in implementing his own teachings, especially his weightings. It has a good bibliography. Lui, "A 12-bit 45-MS/s, 3-mW Redundant...", JSSC, Nov 2011 was also a good read.

I had to derive my own calibration procedure since I couldn't find a published one, but the papers describe in general terms how it needs to be done.

Title: Re: Redundancy vs Calibration
Post by RobG on Oct 31^st, 2014, 8:04am

Sx_cut wrote on Oct 30^th, 2014, 12:40am:

Should we not deduce from here that ADC is more likely to generate errors during the LSB cycles of SAR scheme and so redundancy must be implemented in the LSB bits instead of MSB bits?

Not really, take a look at the MIT Thesis I just referenced to see how redundancy is used.

Title: Re: Redundancy vs Calibration
Post by RobG on Oct 31^st, 2014, 8:05am

RobG wrote on Oct 31^st, 2014, 8:01am:

I'm working that problem right now with a 12b. The ADC is much easier to calibrate digitally if you use redundancy since you can force the ADC to take two paths and then apply digital correction to make the two paths give the same result.

Redundancy is awesome :D. For example, doing a 12 bit conversion with 15 comparisons can (if done correctly) allow very large errors for all but the last two comparisons. Therefore,
1) Your reference doesn't have to settle completely,
2) Your comparator can be very noisy and simple (i.e. fast latch), and
3) Offset differences between stages isn't important so you can use a fast latch for each of the stage

But remember these don't apply to your last two comparisons - they need a low noise comparator.

In addition, cap mismatches can be on the order of 25%, but they do have to be accounted for digitally, whereas the other errors require no digital correction.

Unfortunately, I haven't found many detailed papers to help me. This MIT Thesis was helpful, but I didn't think he did a good job in implementing his own teachings, especially his weightings. Lui, "A 12-bit 45-MS/s, 3-mW Redundant...", JSSC, Nov 2011 was also a good read. Be sure and look at their references.

I had to derive my own calibration procedure since I couldn't find a published one, but the papers describe in general terms how it needs to be done.