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Design Languages >> Verilog-AMS >> how to delay a signal
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Message started by jagadeesh on Oct 29^th, 2014, 7:52am

Title: how to delay a signal
Post by jagadeesh on Oct 29^th, 2014, 7:52am

how to delay a signal dynamically...suppose some integer is there and depending on its value..i have to delay input signal...

Title: Re: how to delay a signal
Post by Geoffrey_Coram on Nov 13^th, 2014, 10:18am

Have you looked at absdelay()? It allows a variable delay, as long as you specify the third argument, which is the maximum delay.

Title: Re: how to delay a signal
Post by Ken Kundert on Nov 14^th, 2014, 5:21am

If the value you want to delay over time is piecewise constant, you should use the transition function to delay it. It is a much lighter function than $absdelay and has better error control. If the value varies continuously with time, then Geoffrey's suggestion of $absdelay() is best.

-Ken