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Design Languages >> Verilog-AMS >> setting an initial voltage for a VeriologA capacitor
https://designers-guide.org/forum/YaBB.pl?num=1416858946

Message started by rosadellavita on Nov 24^th, 2014, 11:55am

Title: setting an initial voltage for a VeriologA capacitor
Post by rosadellavita on Nov 24^th, 2014, 11:55am

Dear all,
I have a question regarding setting the initial voltage for a node in VerilogA, I created a VerilogA capacitor and connected it to my circuit and I want to set the initial voltage of this capacitor depends on the status of another signal, if that signal is 1 V so the initial voltage should be 1, if not the initial voltage should be 0. I know that I can set the ic from the Spectre simulation but I'm looking to control its status through the VerilogA code.
I tried to do it through @(initial_step) but it doesn't work!
Any idea?
Thank you in advance,
Rosa

Title: Re: setting an initial voltage for a VeriologA capacitor
Post by boe on Nov 25^th, 2014, 1:22am

Rosadellavita,
what did you try? Note these hints.
- B O E
PS: for tran simulation, you need to define the initial conditions in the dc/ic simulation.

Title: Re: setting an initial voltage for a VeriologA capacitor
Post by Geoffrey_Coram on Jan 5^th, 2015, 1:06pm

I suspect you have a problem with value retention (look in the LRM); if you contribute a voltage V(t,b) in the initial_step but then contribute a current I(t,b) in the main body, then the current contribution wins.