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Design >> High-Power Design >> Bury layer in BCD process?
https://designers-guide.org/forum/YaBB.pl?num=1421250255

Message started by ywguo on Jan 14^th, 2015, 7:44am

Title: Bury layer in BCD process?
Post by ywguo on Jan 14^th, 2015, 7:44am

Hi Guys,

I heard that all BCD process has bury layer? What's the use of the bury layer?

Best regards,
Yawei

Title: Re: Bury layer in BCD process?
Post by sheldon on Feb 9^th, 2015, 3:52pm

Y,

More info would be good. If it is the N+ buried layer underneath the
npn transistor, then it serves several functions:
1) Lower collector resistance of the npn, lower collector resistance
means lower saturation voltage.
2) It suppresses the beta of the parasitic vertical pnp formed by
the p-base, E, n-collector, B, and p-wafer, C. The idea is that
if the base is more highly doped than the emitter, then Beta
will be low suppressing latch-up and minimizing current
injection into the substrate during saturation.
3) N buried layer also prevents the base depletion region from
reaching the substrate, punchthrough, at high Vcb.

Now if you meant the buried layer under a vertical PNP, that is,
a different thing :-)

Sheldon

Title: Re: Bury layer in BCD process?
Post by ywguo on Feb 19^th, 2015, 7:05pm

Sheldon,

Thank you very much.

I am not familiar with Bipolar process or BCD process. I have never thought of the parasitic vertical pnp and latch-up related to the npn transistors.

Would you please recommend any literature about BCD process, including the effects of parasitic devices on circuit design? Thanks.

Yawei