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Design >> RF Design >> onchip 1:5 balun
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Message started by vlsi_design on Jan 14^th, 2015, 7:30pm

Title: onchip 1:5 balun
Post by vlsi_design on Jan 14^th, 2015, 7:30pm

Hi,

I want to design an onchip 1:5 balun. Can anyone suggest me books or IEEE papers?

Title: Re: onchip 1:5 balun
Post by loose-electron on Jan 19^th, 2015, 12:59pm

IEEE MTT research time. There are a bunch out there go search that journal.
Might be stuff in IEEE JSSC also but I would wager that MTT will have more.

Title: Re: onchip 1:5 balun
Post by totowo on Jan 21^st, 2015, 6:52pm

You can use 3:4 turn ratio, with 3 parallel and 4 series.

Too large turn ratio will decrease the coupling coefficient k.

In my opinion, the best on-chip transformer paper is
<Monolithic Transformers for Silicon RF IC Design> by J. R. Long, Vol 35, No. 9, JSSC 2000

vlsi_design wrote on Jan 14^th, 2015, 7:30pm:

Hi,

I want to design an onchip 1:5 balun. Can anyone suggest me books or IEEE papers?

Title: Re: onchip 1:5 balun
Post by vlsi_design on Feb 8^th, 2015, 11:58pm

Hi loose-electron & totowa,

Thank you for your suggestions.

I have designed the balun in Cadence virtuoso layout. I want to export it to HFSS for EM simulation by exporting the .gds file. Can anyone provide me step by step tutorial for EM simulation in HFSS?

Title: Re: onchip 1:5 balun
Post by nazgul on Mar 2^nd, 2015, 4:20am

Designing a 1:5 balun with a good coupling coupling coefficient is very tough. Ultimately, it boils down to the trade-off between circuit area and coupling coefficient k.
Care to provide the details of the inductance of the windings that you are willing to target, that might help me in pointing you in the right direction??
For good understanding of on-chip balun, you can read the following links

http://marco.stanford.edu/swong/Haitao.pdf
http://smirc.stanford.edu/papers/IEDM98s-mohan.pdf