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Design Languages >> Verilog-AMS >> verilog ams rlc circuit
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Message started by ranjang on Jan 14^th, 2015, 11:07pm

Title: verilog ams rlc circuit
Post by ranjang on Jan 14^th, 2015, 11:07pm

Hi,

I am just writing code series rlc circuit like below.

module series_rlc(p,n);
inout p,n;
electrical p,n;
parameter r=1;
parameter l=1u;
parameter c=1u;
real vr;
real vl;
real vc;
analog
begin
V(p,n)<+r*I(p,n);
vr=r*I(p,n);
V(p,n)<+ l*ddt(I(p,n));
vl=(l*ddt(I(p,n)));
V(p,n)<+(1/c)*idt(I(p,n));
vc=(1/c)*idt(I(p,n));
end

But when I check vl in waves it is always showing zero.
I've two questions
1>why the values of vl is zero if I apply a dc or pulse voltage source with enough high and low pulse (around 10 us high and 10 us low on p)
2>what will this vr,vl,and vc values display will it give voltage across resistor,voltage across inductor,voltage across capacitor individually or something else.

Title: Re: verilog ams rlc circuit
Post by Geoffrey_Coram on Jan 16^th, 2015, 12:02pm

Quote:

V(p,n)<+(1/c)*idt(I(p,n));

Did you read the LRM's restrictions on idt() ?

Quote:

When used in DC or IC analyses, idt() returns the initial condition (ic) if specified. If [the initial condition is] not specified, the idt operator must be contained within a negative feedback loop that forces its argument to zero. Otherwise the output of the idt operator is undefined.

I'm also not quite sure what your simulator is doing; you have specified your circuit as, effectively, a current-controlled voltage source. Then, you say you "apply a dc or pulse voltage." This creates a topology error, because you have a loop of rigid branches (voltage sources).

Title: Re: verilog ams rlc circuit
Post by Ken Kundert on Jan 16^th, 2015, 5:05pm

This appears to be a valid implementation of a series RLC. There should be no topology errors if you drive it with a voltage source, nor should there be any concerns about the initial condition on the capacitor, though you can specify an initial condition if you like.

As to why vl is zero, it should not be if I(p,n) is changing. It is easy to check whether the results are correct. To do so, simply observe I(p,n), calculate the time derivative, multiply by l, and see it matches the value of vl.

-Ken

Title: Re: verilog ams rlc circuit
Post by ranjang on Feb 3^rd, 2015, 4:46am

Hi Ken,
I see that ddt(I(p,n)) is zero even though I(p,n) is not constant.

I am running the simulation with cadence simulator(ncsim+ultrasim command line) with testbench.scs file like below

simulator lang=spectre

ahdl_include "series_rlc.vams"

V1 (p 0) vsource type=pulse val0=0 val1=3 delay=0 rise=0.05n fall=0.05n width=15u period=30u
simulator lang=spice
.tran 1ns 100us

Title: Re: verilog ams rlc circuit
Post by Ken Kundert on Feb 3^rd, 2015, 1:44pm

Try it without ultrasim.