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Design Languages >> Verilog-AMS >> Verilog-AMS Aysnchronous reset of ring-oscillator phase
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Message started by sal on Feb 3^rd, 2015, 1:42pm

Title: Verilog-AMS Aysnchronous reset of ring-oscillator phase
Post by sal on Feb 3^rd, 2015, 1:42pm

I'm fairly new to Verilog-AMS and trying to model a gated ring-oscillator. I'd like to be able to freeze, reset and then re-enable the oscillator with the reset phase using input signals. I generate the phase using

Code:

phase = 2*`M_PI*idtmod(freq*fv,0.0,1.0,-0.5);

and my oscillator output is

Code:

V(OUT) <+ offset + ampl*sin(phase);

where frequency is my output frequency and fv is a variable I set depending on the crossing of enable. Once the enable signal goes low, fv becomes 0 and the state of the ring-oscillator is frozen. When enable goes high, the phase continues to integrate.

I have tried to apply a reset of the phase by detecting the crossing of my reset signal but since idtmod is outside of this, the phase of the oscillator always returns to the phase it was at before I froze its state - rather than continue from the reset state.

I'd much appreciate advice on the following - Whether it is possible to reset the phase of idtmod? And if not, is there another way to model a ring-oscillator with this function using verilog-ams?

Title: Re: Verilog-AMS Aysnchronous reset of ring-oscillator phase
Post by Ken Kundert on Feb 3^rd, 2015, 1:51pm

Perhaps consider a discrete event implementation using disable. Take a look at the synchronouse oscillator found at http://verilogams.com/refman/modules/discrete-procedural/misc.html for inspiration.

-Ken

Title: Re: Verilog-AMS Aysnchronous reset of ring-oscillator phase
Post by boe on Feb 5^th, 2015, 3:44am

sal wrote on Feb 3^rd, 2015, 1:42pm:

...
I'd much appreciate advice on the following - Whether it is possible to reset the phase of idtmod? And if not, is there another way to model a ring-oscillator with this function using verilog-ams?

If you cannot use Ken's suggestion for your application and you need an analog oscillation, I'd suggest to add a phase offset, which changes on reset, e.g.
Code:

V(OUT) <+ offset + ampl*sin(phase - phase_offset);

- B O E

Title: Re: Verilog-AMS Aysnchronous reset of ring-oscillator phase
Post by sal on Feb 6^th, 2015, 1:42am

Thanks, I managed to get the behavior I wanted by calculating a phase offset using @cross and then subtracting this from the current phase of the oscillator.