The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> RF Simulators >> Any advice for PSS converge?
https://designers-guide.org/forum/YaBB.pl?num=1423551101

Message started by sharpmental on Feb 9^th, 2015, 10:51pm

Title: Any advice for PSS converge?
Post by sharpmental on Feb 9^th, 2015, 10:51pm

I am building a Verilog-A model for BUCK circuit. I am using spectre and spectreRF.
In transient simulation it works. I want to show how verilog-A works in PSS simulation, but it is hard to make it converge in PSS simulation.

1. I use abstime to generate PWM signal. So the PWM_clk module is markded with (* instrument_model*).
2. I also use absdelay to generate a nonoverlap switch signal. So the NonOverlap module is markded with (* instrument_model*).
3. if I open the loop and set the feedback voltage, it converged in PSS.
4. In transient, its stability is proved, reasonable small ringing with load/input step.

One warning is on the compensate net. It has 10nF compensation cap to GND. And the GM stage model has limited rout and its output current is limited with tanh function. I don't see how the simulator would calculate this net to be Giga volt.

Is there any general advise?

Title: Re: Any advice for PSS converge?
Post by sharpmental on Feb 10^th, 2015, 10:54pm

Now I can loss some tolerance to make it converge. But the AC/STB result is wrong.
The structure is in the attached picture. The compensation net work is not shown there.
I checked the PSS result, it seems most net are in their correct value.

Title: Re: Any advice for PSS converge?
Post by sharpmental on Feb 10^th, 2015, 10:56pm

But the stb and ac (break ac at fb net) result is all like this:

Title: Re: Any advice for PSS converge?
Post by Frank Wiedmann on Feb 11^th, 2015, 12:32am

I suggest that you take a look at http://www.designers-guide.org/Forum/YaBB.pl?num=1189658426.

Title: Re: Any advice for PSS converge?
Post by rfidea on Feb 14^th, 2015, 2:21pm

Maybe kicking in open doors, but Cadence helpdesk says that 95% of all their PSS convergence questions is solve by longer tstab... Maybe worth trying.

Title: Re: Any advice for PSS converge?
Post by sheldon on Feb 15^th, 2015, 6:01pm

RFIdea,

The suggestion for longer tstab is valid. However, DC-to-DC
Converters provide some unique challenges. Other areas to
consider and investigate:

1) It is difficult to tell from the block diagram, but the clock
generator needs to have some delay so both power devices
are not on at the same time. Improper timing can generate
large current spikes at the instant of switching resulting in
convergence issues. Typically, real power devices would also
be unhappy at the high current density.

2) If you are including effects such as the power supply bond wire,
then the power supply bypass network should be included. Since
a DC-to-DC converters have negative resistance at the power
supply input -R*L can oscillations that result in convergence
issues.

3) Yes, loosening tolerances is also an approach that I use when
simulating DC-to-DC Converters, however, you should check
the waveforms to verify that they are correct, and periodic.

Rather than generic longer tstab, run a transient simulation and
look at the duty cycle of the DC-to-DC converter at the output of
the comparator and set tstab based on the settling of the duty cycle.

Modeling of DC-to-DC Converters is not trivial. However if you
careful, the results can be useful.

Sheldon

Title: Re: Any advice for PSS converge?
Post by Ken Kundert on Feb 18^th, 2015, 12:21pm

You have a hidden state problem. Using instrument_module does not make the hidden state problem go away, it just disables the hidden state warning and allows the analysis to continue.

I don't know why $abstime would raise a hidden state warning. It is clearly not state. But using absdelay is asking for trouble. I recommend you reforumulate your model to avoid use of the absdelay function.

-Ken

Title: Re: Any advice for PSS converge?
Post by sharpmental on Mar 3^rd, 2015, 6:40pm

Hi Sheldon, Ken,

Thanks for your idea.

I use a nonoverlap block to generate clock edge, so as in the real circuit, both switch won't open at the same time.
This block is where I have to use the "instrument" declare.

I read from Cadence papers, it says the function absdelay is not supported in PSS simulation. So i think this module has to be "instrument" block.

Here is the main code of my nonoverlap module:

analog begin

@(initial_step) begin
polar1 = V(in, gnd)>vth?1:0;
polar2 = polar1;
end

V(net1, gnd) <+ absdelay(V(in, gnd), overlaptime*0.5);
polar1 = V(in, gnd)>vth?1:0;
polar2 = V(net1, gnd)>vth?1:0;

V(out, gnd) <+ V(vcc, gnd)*(polar1&&polar2);
V(outb, gnd) <+ V(vcc, gnd)*(!(polar1||polar2));

end

Title: Re: Any advice for PSS converge?
Post by Ken Kundert on Mar 3^rd, 2015, 9:42pm

You cannot use absdelay, regardless of whether you label the module as an instrument module or not. Replace it with an RC delay.

-Ken

Title: Re: Any advice for PSS converge?
Post by sharpmental on Mar 16^th, 2015, 11:29pm

Ken,

Yes, with the RC delay. this module could run PSS now. I also changed some other modules with this method.
Now, I still has the hidden state problem in the PWM signal block. It should generate a ramp up signal with certain period.
I think about it for several days. It seems I have to save the "state" in a variable so to tell the voltage(current) should increase(charge) or decrease (discharge), that cause the hidden state problem.

Do you give me some suggestions on such period signals?

Title: Re: Any advice for PSS converge?
Post by sharpmental on Mar 16^th, 2015, 11:30pm

Here is my code to describe it as current charge:

PWMvol = PWMref>V(VCC, GND)?V(VCC, GND):PWMref;

@(cross(V(VPWM, GND), -1)) begin
slope = PWMvol/(cycle-falltime);
end

@(cross(V(VPWM, GND)-PWMvol, +1)) begin
slope = -PWMvol/falltime;
end

V(VPWM,GND) <+ idt(slope, 0);

Title: Re: Any advice for PSS converge?
Post by sharpmental on Mar 16^th, 2015, 11:32pm

And here is the code to describe it as voltage:

PWMvol = PWMref>V(VCC, GND)?V(VCC, GND):PWMref;

@(timer(0, cycle)) begin
slope = PWMvol/(cycle-falltime);
wstart = $abstime;
polar = 1;
end

@(timer(cycle-falltime, cycle)) begin
slope = -PWMvol/falltime;
wstart = $abstime;
polar = -1;
end

xout = (1+polar)*0.5*slope*($abstime- wstart)+(1-polar)*0.5*(2.5 + slope*($abstime- wstart));

V(VPWM) <+ xout;
end

Both version use variable to save state, so both failed in RF. :'(

Title: Re: Any advice for PSS converge?
Post by Ken Kundert on Mar 17^th, 2015, 11:29am

To eliminate hidden state, you need to eliminate the possibility that a variable is not assigned a value before it is used. So, you can use event statements, but you should not assign values to variable within them. This limitation can make modeling very difficult. But I have found that if you are creative, you can often work around this limitation.

If I were you I would recommend you try using idtmod. With idtmod you can easily make a sawtooth wave without hidden state. Now, you appear to want a triangle wave rather than a sawtooth, but you can get a symmetric triangle wave by passing a bipolar sawtooth through an absolute value function. By adding an offset, and replacing the absolute value with an if statement that scales the signal differently for each polarity, you should be able to build an asymetric triangle wave generator that is free of hidden state.

When you get it please share it. If it looks robust and generally useful, I will add it to the models page.

-Ken

Title: Re: Any advice for PSS converge?
Post by sharpmental on Mar 18^th, 2015, 10:20pm

Hi Ken,

Yes, i got it now. There is really different direction to think about it.

1st I try to use 2 idt and idtmod. It works but I find when the simulation goes to 5mS or more, some error accumulated. The PWM signal either goes higher and higher or lower and lower. I am not sure if it is the simulator or something else wrong in my system.

Then from your explain, using $abstime should be OK for RF simulation. So I think I can use the operator % to check the time instead of save the "current start time".

Here is my code:

// VerilogA for dc_pwm, veriloga

`include "constants.vams"
`include "disciplines.vams"
module dc_pwm(VPWM, GND, VCC);
output VPWM;
electrical VPWM;
input GND;
electrical GND;
input VCC;
electrical VCC;

parameter real cycle = 20u;
parameter real falltime = 1u;
parameter real PWMref = 2.5;
parameter integer DEBUG = 0;

real xout;
real slope;
real wstart;
real wtime;
real polar;

real PWMvol;

analog begin
@(initial_step) begin
PWMvol = PWMref>V(VCC, GND)?V(VCC, GND):PWMref;
wstart = 0;
wtime = 0;
polar = 1;
end

PWMvol = PWMref>V(VCC, GND)?V(VCC, GND):PWMref;//the high level of PWM singal

wstart = $abstime-($abstime%cycle); //cycle start
wtime = $abstime%cycle; //remain time
polar = (wtime<(cycle-falltime))?1:-1; // rising or falling part
slope = (polar>0)?(PWMvol/(cycle-falltime)):(-PWMvol/falltime); // slope

xout = (1+polar)*0.5*slope*($abstime- wstart)+(1-polar)*0.5*(PWMvol + slope*($abstime- wstart - cycle + falltime));

V(VPWM) <+ xout;

@(final_step) begin
$strobe("Module = %M, slope = %g, wtime = %g, wstart=%g, time is %g", slope, wtime, wstart, $abstime);
end
end

endmodule

Title: Re: Any advice for PSS converge?
Post by sharpmental on Mar 18^th, 2015, 10:26pm

Now my BUCK model works in PSS+PSTB, without any "instrument_module" declare.
But the PSTB and PAC result is still wrong. :-[
There is still no gain, phase is flat at 180C.
So this is still "on going".

Title: Re: Any advice for PSS converge?
Post by Frank Wiedmann on Mar 19^th, 2015, 5:45am

Did you take a look at my earlier reply (#3)?

Title: Re: Any advice for PSS converge?
Post by sharpmental on Mar 23^rd, 2015, 10:09pm

Hi Frank,

Yes, I did. I think that ticket means: "the input and output shall have a smooth relation".
I reviewed my code, I "feel" they are, but can not be 100% sure due to many switching behavior of DC-DC itself.

However, i think the "smooth behavior" requirement is conditional because I have done switching cap amp and chopper amp model. The way I describe it is obviously not "smooth" but they work on PSS/PSTB.

Title: Re: Any advice for PSS converge?
Post by Ken Kundert on Mar 23^rd, 2015, 10:40pm

To debug it, you need to treat it as a simple signal tracing problem. You inject a signal and see where it is blocked. If you show us the module that blocks the signal, we might be able to help.

-Ken

Title: Re: Any advice for PSS converge?
Post by sharpmental on Mar 24^th, 2015, 7:10pm

I have to find a new job so i am not in a mood to work these days. >:(
Here is the model I build.
This picture show my top level testbench.
The inductor is 22uH and the load cap is 20~47uF.
The compensation use a 10nF external cap on the output of the gm style EA.

Title: Re: Any advice for PSS converge?
Post by sharpmental on Mar 24^th, 2015, 7:11pm

And, the controller include these blocks:

Title: Re: Any advice for PSS converge?
Post by sharpmental on Mar 24^th, 2015, 7:12pm

So this is a simple Voltage mode control.
And, here is the pack of all verilogA code.

it would be good to hear your advise so I can make this work.

Thanks.