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Design Languages >> Verilog-AMS >> VerilogA in Cadence
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Message started by rosadellavita on Feb 11^th, 2015, 1:50pm

Title: VerilogA in Cadence
Post by rosadellavita on Feb 11^th, 2015, 1:50pm

Dear all,
Regarding the image I attach below, all these blocks in the circuit are VerilogA blocks, I need the signal from the left side to pass through all the blocks to get the output in the right side, actually I have two data files inside the block , which is in the left side, I want to read the first file only to get the output in the right side then go back again to the same verilogA block in the left side to read the second file to get the output related to it, then I use both results to calculate a certain error, then use this error to increase/decrease some variables inside the block and repeat the same steps again until the error is minimized to a certain value, can I control the simulation to do that?

If not, is there a way to save the same circuit under another name and past it beside the original one and apply the second file as an input to it and change the relevant variables without affecting the same variables in the original circuit? or I should start to save as all the VerilogA blocks under another names first before start the simulation using this way? since the figure I attach is only a small portion of my big circuit.

I'll appreciate any help.

Thank you in advance,