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Design >> Mixed-Signal Design >> Time to Digital Conveter - GRO
https://designers-guide.org/forum/YaBB.pl?num=1424970200

Message started by Dshoter on Feb 26^th, 2015, 9:03am

Title: Time to Digital Conveter - GRO
Post by Dshoter on Feb 26^th, 2015, 9:03am

Hi. I'm trying to implement a Time to Digital Converter based on Vernier-Gated-Ring-Oscillator. My guide for this work is the following paper: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6271835&queryText%3DA+90nm+CMOS+digital+PLL+based+on+Vernier+Gated+RIng+Oscillator+TIme+to+Digital+Converter.
Currently, I'm only working with the flip-flop and GROs.
After dimension of the flip-flop and the GROs, I am having some trouble doing the simulations: When I change the frequency of the Slow Line (or Fast Line), it will affect the free running frequency of the Fast Line (or the Slow Line). I think that it is due to the Flip-flop, that provides "dinamyc" capacitive charge to the inverters.. Any ideas how to controll it?
Another issue I would like to address, is the size of the invertes in both lines; I'm trying to balance the load that each line "sees" from the flip flops, then making the difference in the oscillation's frequency by turning on or off the NMOS caps.. Any one has a better suggestion about this?
I'm working with Cadence Virtuoso and TSMC 90nm.

I would like to thank you for your time.

With best regards.