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Simulators >> Circuit Simulators >> Simulating digital filter using Cadence Virtuoso?
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Message started by jdp on Mar 12^th, 2015, 6:34am

Title: Simulating digital filter using Cadence Virtuoso?
Post by jdp on Mar 12^th, 2015, 6:34am

Hi,

Is there any way to simulate the frequency response of digital filters using Cadence Virtuoso? (like AC or PAC analyses done for analog filters)

Actually, I am trying to realize a delta-sigma ADC in Cadence, which consists of a (digital) decimation filter.

Can anybody give any idea how to simulate the performance of this digital decimation filter in Cadence?

Title: Re: Simulating digital filter using Cadence Virtuoso?
Post by Ken Kundert on Mar 12^th, 2015, 6:05pm

No. Well, if the decimation filter is represented with transistors, it would be possible to use SpectreRF to simulate the transfer functions, but it would be extremely expensive. Generally the decimation filter would be represented as Verilog RTL, and Verilog simulators cannot do AC analyses.

-Ken

Title: Re: Simulating digital filter using Cadence Virtuoso?
Post by jdp on Mar 12^th, 2015, 7:38pm

Ken Kundert wrote on Mar 12^th, 2015, 6:05pm:

...if the decimation filter is represented with transistors, it would be possible to use SpectreRF to simulate the transfer functions...

THANK YOU Ken for your helpful reply! I get that using Verilog is the best way... :)

But, for the time-being, if I wish to simulate the decimation filter in SpectreRF, can you please suggest which particular analysis to choose? - should it be periodic transfer function (PXF) analysis ? (but, it is a small signal analysis, will it be valid here?....also, there are multiple output lines!) :-?

Any suggestion will be very helpful.

Title: Re: Simulating digital filter using Cadence Virtuoso?
Post by Ken Kundert on Mar 13^th, 2015, 1:45pm

I take it back. I don't think its possible to use SpectreRF for this task. SpectreRF applies a small-signal to the input, and a small-signal by definition cannot switch a digital input. Occasionally people use SpectreRF on digital circuits to extract jitter. In that case a small signal can impact the timing of an edge crossing, but in this case you need it to actual switch the input, and a small signal cannot do that.

I think the only answer is some kind of system simulator.

-Ken

Title: Re: Simulating digital filter using Cadence Virtuoso?
Post by sheldon on Mar 13^th, 2015, 5:22pm

Ken,

A hypothetical question, if you modeled the transfer function using
ideal blocks: summers, integrators (for delay), and integer
mathematics (represented the signal as an integer), do you
think that the frequency response of the transfer function could
be simulated?

Sheldon

Title: Re: Simulating digital filter using Cadence Virtuoso?
Post by Ken Kundert on Mar 13^th, 2015, 8:48pm

No. The definition of a 'small signal' is that the signal is so small that any nonlinear behavior it causes can be and is neglected. By extension, a small signal cannot cross a threshold, and so cannot cause switching behavior. In the case you mentioned, you represent signals with integers. You need a signal to cross a threshold to get an integer value to switch, and small signals never cross thresholds.

In the back of my mind, when I first answered, I was thinking about switched-capacitor circuits. Small-signal analysis generally works fine on switched-capacitor circuits because the signals are continuous values (real valued). However, small signal analysis breaks down at a comparator or quantizer because small signals cannot cross thresholds.

-Ken

Title: Re: Simulating digital filter using Cadence Virtuoso?
Post by boe on Mar 16^th, 2015, 3:07am

Jdp,
a z-domain filter in Verilog-A should do it - at least in Spectre AC + tran simulations.
- B O E