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https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> $bound_step not working https://designers-guide.org/forum/YaBB.pl?num=1426479908 Message started by cktdesigner on Mar 15th, 2015, 9:25pm |
Title: $bound_step not working Post by cktdesigner on Mar 15th, 2015, 9:25pm Hi, I am trying to check whether my dual-modulus prescaler (divide by 2 or 3) is working correctly. It is comprised entirely of models and no circuit elements. I am using IC615 and AMS Simulator to do this check by running a transient analysis to do this check. The schematic of of the the circuit is attached. This is just the circuit given in Razavi's book (2nd Edn.) RF Microelectronics. The original circuit is also attached for your reference. The test-bench I am using to test the circuit is also attached. Code for the D-FF is as follows: `include "constants.vams" `include "disciplines.vams" module adff (q, qb, clk, d); output q; voltage q; // Q output output qb; voltage qb; // Q bar output input clk; voltage clk; // Clock input (edge triggered) input d; voltage d; // D input real td; real tt; real vh; real vl; real vth; integer dir; real state; analog begin td = 0; tt = 0; vh = 1; vl = 0; vth = (vh + vl)/2; dir = +1; @(cross(V(clk) - vth, dir)) state = (V(d) > vth); V(q) <+ transition( state ? vh : vl, td, tt ); V(qb) <+ transition( state ? vl : vh, td, tt ); $bound_step(1p); end endmodule Code for the OR gate is as follows: `include "constants.vams" `include "disciplines.vams" module aor (out, in1, in2); output out; voltage out; input in1, in2; voltage in1, in2; real vh; // output voltage in high state real vl; // output voltage in low state real vth; // threshold voltage at inputs real td; // delay to start of output transition real tt; // transition time of output signals analog begin vh = 1; vl = 0; vth = (vh + vl)/2; td = 0; tt = 0; @(cross(V(in1) - vth) or cross(V(in2) - vth)) ; $bound_step(1p); V(out) <+ transition( ((V(in1) > vth) || (V(in2) > vth)) ? vh : vl, td, tt ); end endmodule Code for the AND gate is as follows: `include "constants.vams" `include "disciplines.vams" module aand (out, in1, in2); output out; voltage out; input in1, in2; voltage in1, in2; real vh; // output voltage in high state real vl; // output voltage in low state real vth; // threshold voltage at inputs real td; // delay to start of output transition real tt; // transition time of output signals analog begin vh = 1; vl = 0; vth = (vh + vl)/2; td = 0; tt = 0; @(cross(V(in1) - vth) or cross(V(in2) - vth)) ; $bound_step(1p); V(out) <+ transition( ((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt ); end endmodule The NOT gate is implemented as a NAND gate whose inputs are both shorted together as one input: The code for the NAND gate is as below: `include "constants.vams" `include "disciplines.vams" module anand (out, in1, in2); output out; voltage out; input in1, in2; voltage in1, in2; real vh; // output voltage in high state real vl; // output voltage in low state real vth; // threshold voltage at inputs real td; // delay to start of output transition real tt; // transition time of output signals analog begin vh = 1; vl = 0; vth = (vh + vl)/2; td = 0; tt = 0; @(cross(V(in1) - vth) or cross(V(in2) - vth)) ; $bound_step(1p); V(out) <+ transition( !((V(in1) > vth) && (V(in2) > vth)) ? vh : vl, td, tt ); end endmodule I input a 2.4GHz as input to the module. I have set MC input as 0 to the module so the module should given an output of divide by 3. OR 800MHz as output. When I simulate the circuit for 42ns I observe that I get the correct output @ 800MHz. However, if I run a transient for 4us I observe that the output is incorrect. Please refer to the attached waveforms for the 42ns and 5us plots. I have done quite a bit of searching here in this board but only observe that $bound_step is the solution to solve this problem. However, I have given $bound_step(1p) in the code as you may notice above. Still, It is of no use and I get incorrect results. Can someone please help tell me why I observe correct output when tran runs for 42ns and not when it runs for 5us? Can someone please help me solve this problem? Thank you. |
Title: Re: $bound_step not working Post by cktdesigner on Mar 15th, 2015, 9:26pm Circuit from Razavi's book attached. |
Title: Re: $bound_step not working Post by cktdesigner on Mar 15th, 2015, 9:28pm Test-bench used to test the module: |
Title: Re: $bound_step not working Post by cktdesigner on Mar 15th, 2015, 9:32pm Input and Output plots for Transient simulation run for 42nsecs. |
Title: Re: $bound_step not working Post by cktdesigner on Mar 15th, 2015, 9:35pm Input and Output plots for Transient simulation run for 5usecs. This is a zoomed-in view of the output. Observe that the output is not correct. |
Title: Re: $bound_step not working Post by boe on Mar 16th, 2015, 3:04am Cktdesigner, are you sure the second simulations writes out all data points? This is a typical mistake causing such behavior. - B O E |
Title: Re: $bound_step not working Post by cktdesigner on Mar 16th, 2015, 3:33am boe wrote on Mar 16th, 2015, 3:04am:
Hi BOE, How do you ensure that all data points are written out? I have not modified anything between the two simulations apart from the run time from 42ns to 5us. Thank you. |
Title: Re: $bound_step not working Post by boe on Mar 16th, 2015, 4:14am Cktdesigner, there are skip & strobe settings in the simulator settings. However, then it should also affect the input clk. So probably the timing tolerance of the cross event is too large (default value probably depends on sim end time). - B O E |
Title: Re: $bound_step not working Post by Ken Kundert on Mar 16th, 2015, 6:36am I believe your problem is not with boundstep, but with transition. Specifically, you are specifying 0 for the transition time. This does not mean that you get a transition time of 0. Rather it indicates that the default transition time should be used. The default transition time is a function of the total simulation time. I don't remember the relationship, but I would guess that the default transition time is something like 0.1% of the total simulation time. That is why your results degraded as you lengthened your simulation time. I recommend that you undo the changes you made to these models. Specifically, remove boundstep and convert the parameters back to being parameters. Then, specify a reasonable transition time. Say, 100ps. In doing so, I think you will find that the simulation speeds up considerably. You should not be using boundstep in this way. It really should only be used in a source that generates a smooth high frequency signal. Practically, this means sinusoidal independent sources and VCOs (think of boundstep as the way that you the modeler inform the simulator about a Nyquist sample rate constraint). Converting all the parameters to be variables causes them to be reassigned on every iteration, which is wasteful and means they cannot be set from the outside. If you really don't want the to be parameters, you would be better served if you convert them to simple numbers. -Ken |
Title: Re: $bound_step not working Post by cktdesigner on Mar 16th, 2015, 7:26am Hi Ken, As always you are right. My problem is solved and simulation is back to being quick. Many thanks for taking time to reply in such a detailed manner. Very helpful! Thank you! |
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